Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

+V3_3
+V3_3
+V3_3
+V12
+V3_3
+V3_3
+V3_3
2N3904_DUAL
+
FWH_PLCC32
FGPI0
FGPI1
FGPI2
FGPI3
DQ7_RFU
DQ6_RFU
DQ5_RFU
ID3
ID2
ID1
FWH0
FWH1
FWH2
FWH3
GND1
GND0
GNDA
VCC1
VCC0
WP
TBL
IC
RST
CLK
FWH4
ID0
DQ4_RFU
RY_BY_RFU
FGPI4
INIT
VPP
VCCA
FIRMWARE HUB
3 2
1
R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
Place C893-895 near pins 1, 25 and 32
FWH
No Jumper
3 - 4
1 - 2
ALL BLOCKS WRITE ENABLE
BLOCK 2-8 PROTECT
TOP BLOCK PROTECT
WP Jumper Settings
68 85
INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD 1.0
11/18/02
2
3
1
4
5
J29
PCIRST_2_N
27,31,61,69
3
2
1
Q1
6
5
4
3
21
20
19
9
10
11
13
14
15
17
26
16
28
25
32
7
8
29
2
31
23
12
18
22
30
24
1
27
U17
R754
470
R745
470
ICH3_LAD0
ICH3_LAD[3:0]
62,69
ICH3_LAD3
ICH3_LAD2
ICH3_LAD1
R753
300
C894
0.1UF 0.1UF
C893 C892
0.1UF
1 2
C1748
4.7UF
ICH3_LFRAME_N
62,69
R_ICH3_INIT_N
3 6
5 2
4 1
Q20
TP_FWH_03_6
R757
4.7K
R756
4.7K
R755
4.7K
R752
1K
R751
4.7K
R750
10K
R749
100
R748
4.7K
R747
4.7K
R746
4.7K
R744
1K
R743
10K
FWH_WP_N
FWH_INIT_N
ICH3_INIT_N
4,6,9,61
FWH_CLK33
80
FWH_J4BIT_1
FWH_J4BIT_4
FWH_IC
FWH_TBL_N
FWH_FGP_14
FWH_FGP_13
FWH_FGP_12
FWH_FGP_11
FWH_FGP_10