64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
44 Order Number: 302402-024
b.Update the associated cache line state information to shared state on
the originating bus (rather than invalid state) in reaction to a BWIL or
BLW.
Status: For the steppings affected, see the Summary Table of Changes.
S76 Control Register 2 (CR2) can be updated during a REP MOVS/
STOS instruction with fast strings enabled
Problem: Under limited circumstances while executing a REP MOVS/STOS string
instruction, with fast strings enabled, it is possible for the value in CR2 to be
changed as a result of an interim paging event, normally invisible to the user.
Any higher priority architectural event that arrives and is handled while the
interim paging event is occuring may see the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is
signaled. Intel has not observed this erratum with any commercially available
software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Table of Changes at the
beginning of this section.
S77 REP STOS/MOVS instructions with RCX >= 2^32 may cause
system hang
Problem: In IA-32e mode using Intel EM64T-enabled processors, executing a repeating
string instruction with the iteration count greater than or equal to 2^32 and a
pending event may cause the REP STOS/MOVS instruction to live lock and
hang.
Implication: When this erratum occurs, the processor may live lock and result in a system
hang. Intel has not observed this erratum with any commercially available
software.
Workaround:Do not use strings larger than 4 GB.
Status: For the steppings affected, see the Summary Table of Changes.
S78 REP MOVS or REP STOS instruction with RCX >= 2^32 may fail
to execute to completion or may write to incorrect memory
locations on processors supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an
REP STOS instruction executed with the register RCX >= 2^32, may fail to
execute to completion or may write data to incorrect memory locations.
Implication: This erratum may cause incomplete instruction execution or incorrect data in
the memory. Intel has not observed this erratum with any commercially
available software.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.