64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update

14 64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S20 XFixedA 16-bit address wrap resulting from a near branch (jump or
call) may cause an incorrect address to be reported to the
#GP exception handler
S21 XXXXXNo FixBus locks and SMC detection may cause the processor to
temporarily hang
S22 Fixed Incorrect physical address size returned by CPUID instruction
S23 XXXXXNo FixIncorrect debug exception (#DB) may occur when a data
breakpoint is set on an FP instruction
S24 XXXXXNo FixxAPIC may not report some illegal vector errors
S25 XXXXXPlan FixEnabling no-eviction mode (NEM) may prevent the operation
of the second logical processor in a Hyper-Threading
Technology enabled boot strap processor (BSP)
S26 XXXXXPlan FixTPR (Task Priority Register) updates during voltage
transitions of power management events may cause a system
hang
S27 XXXXNo FixInteractions between the instruction translation lookaside
buffer (ITLB) and the instruction streaming buffer may cause
unpredictable software behavior
S28 XXX FixedSTPCLK# signal assertion under certain conditions may
cause a system hang
S29 XXXXXNo FixIncorrect duty cycle is chosen when on-demand clock
modulation is enabled in a processor supporting
Hyper-Threading Technology
S30 XXXXXNo FixMemory aliasing of pages as uncacheable memory type and
write back (WB) may hang the system
S31 XXXXXNo FixUsing STPCLK# and executing code from very slow memory
could lead to a system hang
S32 XXXXXNo FixProcessor provides a 4-byte store unlock after an 8-byte load
lock
S33 Duplicate Erratum: see S5
S34 XXXXXPlan FixExecution of IRET and INTn instructions may cause
unexpected system behavior
S35 XXXXXNo FixData breakpoints on the high half of a floating-point line split
may not be captured
S36 XXXXXNo FixMachine Check Exceptions may not update Last-Exception
Record MSRs (LERs)
S37 XXXXXNo FixMOV CR3 performs incorrect reserved bit checking when in
PAE paging
S38 XXXXXNo FixStores to page tables may not be visible to pagewalks for
subsequent loads without serializing or invalidating the page
table entry
S39 XFixedA split store memory access may miss a data breakpoint
S40 XFixedEFLAGS.RF may be incorrectly set after an IRET instruction
S41 XFixedWriting the Echo TPR disable bit in IA32_MISC_ENABLE
may cause a #GP fault
S42 XFixedIncorrect access controls to
MSR_LASTBRANCH_0_FROM_LIP MSR registers
Errata (Sheet 2 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata