64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

14 64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update
Summary Table of Changes
J57 X X No Fix Control Register 2 (CR2) can be updated during a REP MOVS/STOS instruction with fast
strings enabled
J58 X X No Fix REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang
J59 X X No Fix An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to
completion or may write to incorrect memory locations on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
J60 X X No Fix An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may
cause a system hang on processors supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
J61 X X No Fix CPUID instruction returns incorrect brand string
J62 X X No Fix Data access which spans both canonical and non-canonical address space may hang
system
J63 X X No Fix Running in System Management Mode (SMM) and l1 data cache adaptive mode may
cause unexpected system behavior when SMRAM is mapped to cacheable memory
J64 X No Fix A#[39:36] always have On Die Termination (ODT) enabled
J65 X X No Fix A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly in the Branch
Trace Store (BTS) memory record or in the Precise Event Based Sampling (PEBS) memory
record
J66 X X Plan Fix It is possible that two specific invalid opcodes may cause unexpected memory accesses
J67 X X
No Fix
At Core-to-bus ratios of 16:1 and above Defer Reply transactions with non-zero REQb
values, may cause a Front Side Bus stall
J68 X X No Fix The processor may issue Front Side Bus transactions up to 6 clocks after RESET# is
asserted
J69 X X No Fix Front Side Bus machine checks may be reported as a result of on-going transactions during
warm reset
J70 X X No Fix Writing the Local Vector Table (LVT) when an interrupt is pending may cause an
unexpected interrupt
J71 X X No Fix The processor may issue multiple code fetches to the same cache line for systems with
slow memory
J72 X X No Fix IRET under certain conditions may cause an unexpected alignment check exception
J73 X X No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address translations.
J74 X X No Fix Writing shared unaligned data that crosses a cache line without proper semaphores or
barriers may expose a memory ordering issue.
J75 X X No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode.
J76 X X No Fix FPU Operand pointer may not be cleared following FINIT/FNINIT.
J77 X X No Fix L2 Cache ECC machine-check errors may be erroneously reported after an asynchronous
RESET# assertion.
J78 X X No Fix The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow Bit is not set
when multiple un-correctable machine check errors occur at the same time.
J79 X X No Fix Debug Status Register (DR6) Breakpoint Condition Detected Flags may be set incorrectly.
J80 X X No Fix A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE.
Errata (Sheet 3 of 3)
No.
A-0/
0F41h
B-0/
0F49H
Plans Errata