64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
34 Order Number: 302402-024
S37 MOV CR3 performs incorrect reserved bit checking when in PAE
paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper
unimplemented address bits. This checking range should match the address
width reported by CPUID instruction 0x8000008. This erratum applies
whenever PAE is enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and
expects a fault may fail. This erratum has not been observed with
commercially available software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S38 Stores to page tables may not be visible to pagewalks for
subsequent loads without serializing or invalidating the page
table entry
Problem: Under rare timing circumstances, a page table load on behalf of a
programmatically younger memory access may not get data from a
programmatically older store to the page table entry if there is not a fencing
operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel
®
Architecture Software
Developer’s Manual for the correct way to update page tables. Software that
conforms to the Software Developer's Manual will operate correctly.
Implication: If the guidelines in the Software Developer's Manual are not followed, stale
data may be loaded into the processor's Translation Lookaside Buffer (TLB)
and used for memory operations. This erratum has not been observed with
any commercially available software.
Workaround:The guidelines in the IA-32 Intel
®
Architecture Software Developer’s Manual
should be followed.
Status: For the steppings affected, see the Summary Table of Changes.
S39 A split store memory access may miss a data breakpoint
Problem: It is possible for a data breakpoint specified by a linear address to be missed
during a split store memory access. The problem can happen with or without
paging enabled.
Implication: This erratum may limit the debug capability of a debugger software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S40 EFLAGS.RF may be incorrectly set after an IRET instruction
Problem: EFLAGS.RF is used to disable code breakpoints. After an IRET instruction,
EFLAGS.RF may be incorrectly set or not set depending on its value right
before the IRET instruction.
Implication: A code breakpoint may be missed or an additional code breakpoint may be
taken on next instruction.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.