64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 31
Errata
Implication: When this erratum occurs, a page fault exception may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J47. Execute disable bit set with AD assist may cause livelock
Problem: If Execute Disable Bit is set and the resulting page requires the processor to set the A and/or D bit
(Access and/or Dirty bit) in the PTE, then the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J48. The execute disable bit fault may be reported before other types of page
fault when both occur
Problem: If the execute disable bit is enabled and both the execute disable bit fault and page faults occur, the
execute disable bit fault will be reported prior to other types of page fault being reported.
Implication: No impact to properly written code since both types of faults will be generated but in the opposite
order.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J49. Writes to IA32_MISC_ENABLE may not update flags for both logical
processors
Problem: On processors supporting HT Technology with Execute Disable Bit feature, writes to
IA32_MISC_ENABLE may only update IA32_EFER.NXE for the current logical processor.
Implication: Due to this erratum, the non-current logical processor may not update its IA32_EFER.NXE bit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J50. Execute disable bit set with CR4.PAE may cause livelock
Problem: If the execute disable bit of IA32_MISC_Enable is set along with the PAE bit of CR4
(IA32_EFER.NXE & CR4.PAE), the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J51. Checking of page table base address may not match the address bit width
supported by the platform
Problem: If the page table base address, included in the page map level-4 table, page-directory pointer table,
page-directory table or page table, exceeds the physical address range supported by the platform
(e.g. 36-bit) and it is less than the implemented address range (e.g. 40-bit), the processor does not
check if the address is invalid.
Implication: If software sets such invalid physical address in those tables, the processor does not generate a page
fault (#PF) upon access to that virtual address, and the access results in an incorrect read or write. If