Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Memory Interface Routing Guidelines
92 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
6.5 Chip Select Routing
The MCH provides eight chip select signals. Two chip selects must be routed to each DIMM
(one for each side). Chip selects for each DIMM must be length matched to the corresponding
clock within ± 875 mils and require parallel termination resistors (Rtt) to DDR VTERM.
NOTES:
1. On a compatible motherboard, use a 33.2 Ω for an E7500 chipset MCH and a 39.2 Ω for an E7501 chipset
MCH.
NOTES:
1. 3-DIMM solution: Treat CS_x6# and CS_x7# as a no connect.
2. Indicated lengths measured from the MCH component pin to the DIMM connector pin.
Table 6-7. Chip Select Routing Guidelines
Parameter 3-DIMM Solution 4-DIMM Solution Reference
Signal Group CS[7:0]#
Topology Point to Point Figure 6-10
Reference Plane Ground Figure 6-5
Trace Impedance (Z
0
) 50 Ω ± 10% 50 Ω ± 10% Table 6-2
Nominal Trace Width 5 mil 5 mil Figure 6-5
Nominal Trace Spacing 15 mil 15 mil Figure 6-5
MCH to DIMM1 Trace Length 4.0" ± 875 mil 7.50" ± 875 mil Figure 6-10
MCH to DIMM2 Trace Length 6.0" ± 875 mil 8.00" ± 875 mil Figure 6-10
MCH to DIMM3 Trace Length 8.0" ± 875 mil 8.75" ± 875 mil Figure 6-10
MCH to DIMM4 Trace Length Not Applicable 10.75" ± 875 mil Figure 6-10
Trace Length - DIMM to Rtt 0.3" to 1.5” 0.1" to 1.5” Figure 6-10
Termination Resistor (Rtt) 39.2
Ω ± 1% / 33.2 Ω ± 1%
1
34.8 Ω ± 1% Figure 6-10
MCH Breakout Guidelines 5/5, < 500 mil 5/5, < 500 mil
Figure 6-10. Chip Select Topology
CS_x0#
CS_x1#
CS_x2#
CS_x3#
CS_x4#
CS_x5#
CS_x6#
CS_x7#
MCH
DDR VTERM (1.25V)
DIMMs
Rtt
MCH to DIMM
DIMM
to Rtt