64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 49
—Intel
®
Xeon™ Processor with 800 MHz System Bus
S93 The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow Bit is not
set when multiple un-correctable machine check errors occur at
the same time.
Problem: When two MC0/MC1 enabled un-correctable machine check errors are
detected in the same internal clock cycle, the highest priority error will be
logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow
bit may not be set.
Implication: The highest priority error will be logged and signaled if enabled, but the
overflow bit in the IA32_MC0_STATUS/ IA32_MC1_STATUS register may not
be set.
Workaround:None identified.
Status: No Fix.
S94 Debug Status Register (DR6) Breakpoint Condition Detected
Flags May be Set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious
breakpoint condition under certain boundary conditions when either:
•A "MOV SS" or "POP SS" instruction is immediately followed by a hardware
debugger breakpoint instruction, or
•Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a
general-detect exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set
incorrectly.
Workaround:None identified.
Status: No Fix.
S95 L2 Cache ECC Machine Check Errors May be erroneously
Reported after an Asynchronous RESET# Assertion
Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC
machine-check errors when cache transactions are in-flight and RESET# is
asserted:-
•Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)
•L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)
Workaround:When a real run-time L2 Cache ECC Machine Check occurs, a corresponding
valid error will normally be logged in the IA32_MC0_STATUS register. BIOS
may clear IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific
errors when IA32_MC0_STATUS does not have its VAL flag set.
Status: For the steppings affected, see the Summary Tables of Changes.