64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 35
Errata
L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will
only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit.
Implication: This erratum can have multiple failure symptoms, including incorrect data in memory. Intel has not
observed this erratum with any commercially available software.
Workaround: Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode control bit
(bit 24) of the IA32_MISC_ENABLES MSR (0x1a0) to 1.
Status: For the steppings affected, see the Summary Table of Changes.
J64. A#[39:36] always have On Die Termination (ODT) enabled
Problem: ODT will be enabled on the end agents and middle agents for signals A#[39:36], resulting in a V
OL
increase, which may create system level timing problems.
Implication: Signal quality analysis should be reviewed for these signals. Systems which do not use signals
A#[39:36] (typically with < 64 GB of addressable memory) are not exposed to this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J65. A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly
in the Branch Trace Store (BTS) memory record or in the Precise Event
Based Sampling (PEBS) memory record
Problem: On a processors supporting Intel EM64T,
• If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value
of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to 0xFFFFFFFF
when they should be 0).
• If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh,
the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to
FFFFFFFFh when they should be 0).
Implication: Intel has not observed this erratum on any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J66. It is possible that two specific invalid opcodes may cause unexpected
memory accesses
Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either
opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the processor
may respond instead, with a load to an incorrect address.
Implication: This erratum may cause unpredictable system behavior or system hang.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J67. At Core-to-bus ratios of 16:1 and above Defer Reply transactions with
non-zero REQb values, may cause a Front Side Bus stall
Problem: Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are met:
1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b,
and
2. The operating bus ratio is 16:1 or higher