64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus 43
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
S93 Debug Status Register (DR6) Breakpoint Condition Detected Flags May be
Set Incorrectly
Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under
certain boundary conditions when either:
• A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger
breakpoint instruction, or
• Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect
exception condition.
Implication: Due to this erratum the breakpoint condition detected flags may be set incorrectly.
Workaround: None identified.
Status: No Fix.