64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 41
Specification Clarifications
Specification Clarifications
There are no new Specification Clarifications for this month.
The Specification Changes listed in this section apply to the following documents:
1. 64-bit Intel
®
Xeon
®
Processor MP with 1 MB L2 Cache Datasheet (Document Number
306751)
2. IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 1: Basic Architecture
(Document Number 253665)
3. IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 2A: Instruction Set
Reference, A-M (Document Number 253666)
4. IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 2B: Instruction Set
Reference, N-Z (Document Number 253667)
5. IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3A: System Programming
Guide (Document Number 253668)
6. IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3B: System Programming
Guide (Document Number 253669)
All Specification Clarifications will be incorporated into a future version of the appropriate Intel
Xeon processor documentation.
J1. Specification Clarification with respect to Time Stamp Counter
In the “Debugging and Performance Monitoring” section (Sections 15.8, 15.10.9 and 15.10.9.3) of
the IA-32 Intel
®
Architecture Software Developer’s Manual Volume 3: System Programming
Guide, the Time Stamp Counter definition has been updated to include support for the future
processors. This change will be incorporated in the next revision of the IA-32 Intel
®
Architecture
Software Developer’s Manual.
15.8 Time-Stamp Counter
The IA-32 architecture (beginning with the Pentium
®
processor) defines a time-stamp counter
mechanism that can be used to monitor and identify the relative time occurrence of processor
events. The counter’s architecture includes the following components:
• TSC flag — A feature bit that indicates the availability of the time-stamp counter. The counter
is available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] =
1.
• IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium
processors) — The MSR used as the counter.
• RDTSC instruction — An instruction used to read the time-stamp counter.
• TSD flag — A control register flag is used to enable or disable the time-stamp counter
(enabled if CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and
Intel
®
Xeon
®
processors) is a 64-bit counter that is set to 0 following a RESET of the processor.
Following a RESET, the counter will increment even when the processor is halted by the HLT