Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 31
Errata
cache at the same time that a prefetch RFO is issued to this address. A boundary condition
exists in the bus logic where the prefetch may be issued on the system bus before the modified
data in the L3 is written back to main memory. Consequently the RFO gets stale data for the
adjacent sector from main memory and fills the cache with this stale data.
Implication: The processor may use stale data from the cache.
Workaround: Disable the Hardware Prefetcher by setting bit 9 in register IA32_MISC_ENABLE - MSR Address
01A0h via the BIOS.
Status: For the steppings effected, see the Summary Table of Changes.
O38 System may hang if a fatal cache error causes bus write line (BWL)
transaction to occur to the same cache line address as an outstanding bus
read line (BRL) or bus read-invalidate line (BRIL)
Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL
transaction to the same cache line address as an outstanding BRL or BRIL. As it is not typical
behavior for a single processor to have a BWL and a BRL/BRIL concurrently outstanding to the
same address, this may represent an unexpected scenario to system logic within the chipset.
Implication: The processor may not be able to fully execute the machine check handler in response to the fatal
cache error if system logic does not ensure forward progress on the system bus under this scenario.
Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery
from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL
transactions is not important. Forward progress is the primary requirement.
Status: For the steppings effected, see the Summary Table of Changes.
O39 Re-mapping the APIC base address to a value less than or equal to
0xDC001000 may cause I/O and special cycle failure
Problem: Re-mapping the APIC base address from its default can cause conflicts with either I/O or special
cycle bus transactions.
Implication: Either I/O or special cycle bus transactions can be redirected to the APIC, instead of appearing on
the front side bus.
Workaround: Use any APIC base addresses above 0xDC001000 as the relocation address.
Status: For the steppings effected, see the Summary Table of Changes.
O40 Erroneous machine check error reported
Problem: An erroneous multi-bit ECC machine check error may occur on HT Technology enabled processors
when both logical processors are in the halt state. In this state, the clocks inside the processor will
be shut off. There is a boundary case where a speculative page walk could be occurring while the
clocks are shut off. This page walk continues after the clocks are turned back on. If the clocks are
off when the page walk is in a specific pipe stage in the machine, an erroneous L2 tag ECC error
may be observed.
Implication: Due to this erratum, an erroneous multi-bit error may be reported in the machine check registers
when machine check is enabled. There is no known impact when machine check is disabled. There
have been no observances of data corruption caused by this issue.
Workaround: It is possible for BIOS to contain a workaround for this issue.
Status: For the steppings effected, see the Summary Table of Changes.
O41 Processor does not flag #GP on non-zero write to certain MSRs
Problem: When a non-zero write occurs to the upper 32 bits of IA32_CR_SYSENTER_EIP or
IA32_CR_SYSENTER_ESP, the processor should indicate a general protection fault by flagging
#GP. Due to this erratum, the processor does not flag #GP.