Intel Xeon Processor MP Specification Update

30 Intel
®
Xeon
®
Processor MP Specification Update
Errata
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O34 CR2 may be incorrect or an incorrect page-fault error code may be pushed
onto stack after execution of an LSS instruction
Problem: Under certain timing conditions, the internal load of the selector portion of the LSS instruction
may complete with potentially incorrect speculative data before the load of the offset portion of the
address completes. The incorrect data is corrected before the completion of the LSS instruction but
the value of CR2 and the error code pushed on the stack are reflective of the speculative state. Intel
has not observed this erratum with commercially available software.
Implication: When this erratum occurs, the contents of CR2 may be off by two, or an incorrect page-fault error
code may be pushed onto the stack.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O35 Hyper-Threading Technology enabled processors may hang in the presence
of extensive self-modifying code
Problem: For multiprocessor platforms, in which HT Technology enabled processors are executing extensive
self modifying code, and branch trace messages are enabled on at least one logical processor, the
system may hang. In this scenario, a processor executing within 1K of code being written to by
another processor may attempt to end this flow, thereby resulting in a hang.
Implication: When this erratum occurs the system will hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O36 Global bit incorrectly set for secondary logical processors in ITLB
Problem: Due to a boundary condition in the translation look-aside buffer logic, the global bit information in
the TLB entry for a mapping belonging to the first logical processor can overwrite the global bit
information for a mapping belonging to the second logical processor. This occurs in the following
scenario:
• The first logical processor misses the ITLB resulting in a page walk.
• The second logical processor also misses the ITLB and generates a page walk.
In certain timing scenarios within the processor, the leftover global bit information from the first
logical processor may overwrite the second logical processor.
Implication: When this erratum occurs, if the page global bit for the second logical processor is overwritten with
a 0b, this will result in performance degradation for the first logical processor. If the page global bit
is incorrectly changed from a 0 to 1, this erratum may result in software failures.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings effected, see the Summary Table of Changes.
O37 Hardware prefetcher may cause stale data to be loaded into the processor
caches
Problem: The processor may use stale data from the cache while the hardware prefetcher is enabled. The
conditions of this erratum are as follows:
• A cache line is stored in the L3 cache in shared state while its adjacent sector is in modified
state. The same cache line and its adjacent sector reside in the L2 cache in the shared and
invalid state, respectively. The cache line and its adjacent sector are being evicted from the L3