Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 5
7 Hub Interface............................................................................................................103
7.1 Signal Naming Convention................................................................................103
7.2 Hub Interface 2.0 Implementation .....................................................................104
7.2.1 Hub Interface 2.0 High-Speed Routing Guidelines ..........................104
7.2.2 Hub Interface 2.0 Generation/Distribution of Reference Voltages ...107
7.2.3 Hub Interface 2.0 Resistive Compensation ......................................108
7.2.4 Hub Interface 2.0 Decoupling Guidelines.........................................108
7.2.5 Unused Hub Interface 2.0 Interfaces................................................108
7.3 Hub Interface 1.5 Implementation .....................................................................109
7.3.1 Hub Interface 1.5 High-Speed Routing Guidelines ..........................109
7.3.2 Hub Interface 1.5 Generation/Distribution of Reference Voltages ...110
7.3.3 Hub Interface 1.5 Resistive Compensation ......................................111
7.3.4 Hub Interface 1.5 Decoupling Guidelines.........................................111
8Intel
®
82870P2 (P64H2) ........................................................................................113
8.1 PCI/PCI-X Design Guidelines............................................................................ 113
8.1.1 General PCI-X Routing Guidelines................................................... 114
8.1.2 PCI/PCI-X Routing Requirements (No Hot-Plug Switch) .................115
8.1.3 PCI/PCI-X Hot-Plug Switch Routing Requirements ......................... 116
8.1.4 Riser Card Topologies......................................................................117
8.1.5 PCI-X Two Devices Down Routing Requirements ...........................119
8.1.6 Clock Configuration ..........................................................................120
8.1.7 Loop Clock Configuration .................................................................121
8.1.8 IDSEL Implementation .....................................................................122
8.1.9 SMBus Address................................................................................122
8.2 Hot-Plug Implementation...................................................................................123
8.2.1 Standard Usage Model..................................................................... 123
8.2.1.1 Hot-Removals .....................................................................123
8.2.1.2 Hot-Insertions ..................................................................... 124
8.2.2 Hot-Plug Switch Implementation ......................................................124
8.2.2.1 Manually-Operated Retention Latch Sensor....................... 125
8.2.2.2 Optional Attention Button....................................................126
8.2.3 LED Indicator Outputs ......................................................................126
8.2.4 Hot Plug Interrupt Routing Requirements ........................................126
8.2.5 Disabling/Enabling an Intel
®
P64H2 Hot-Plug Controller .................127
8.2.5.1 Hot-Plug Strapping Options ................................................127
8.2.5.2 Hot-Plug Registers’ Visibility...............................................127
8.2.6 Single-Slot Parallel Mode .................................................................127
8.2.6.1 Required Additional Logic...................................................127
8.2.6.2 PCI Clock............................................................................ 127
8.2.6.3 Debounced Hot-Plug Switch Input...................................... 128
8.2.6.4 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins...........128
8.2.6.5 Tri-State Buffer or 2:1 Multiplexer for HPx_SLOT[2:0] .......128
8.2.6.6 Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode.129
8.2.6.7 SMBus Address Considerations .........................................130
8.2.6.8 Pull-Ups/Pull-Downs in Single-Slot Parallel Mode..............130
8.2.6.9 Reference Schematic for Single-Slot Parallel Mode...........131
8.2.7 Dual-Slot Parallel Mode.................................................................... 132
8.2.7.1 Required Additional Logic...................................................132
8.2.7.2 Debounced Hot-Plug Switch Input...................................... 132
8.2.7.3 Comparator Circuit for PCIXCAP1/PCIXCAP2 Pins...........132