Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

DS2119M
-R1
-R2
-R3
-R4
-R5
-R6
-R7
-R8
+R1
+R2
+R3
+R4
+R5
+R6
+R7
+R8
+R9
DIFF_CAP
HSGND2
HSGND1
GND
D_SNS
VREF
M_S
ISO
-R9
TPWR1
TPWR0
DS2119M
-R1
-R2
-R3
-R4
-R5
-R6
-R7
-R8
+R1
+R2
+R3
+R4
+R5
+R6
+R7
+R8
+R9
DIFF_CAP
HSGND2
HSGND1
GND
D_SNS
VREF
M_S
ISO
-R9
TPWR1
TPWR0
DS2119M
-R1
-R2
-R3
-R4
-R5
-R6
-R7
-R8
+R1
+R2
+R3
+R4
+R5
+R6
+R7
+R8
+R9
DIFF_CAP
HSGND2
HSGND1
GND
D_SNS
VREF
M_S
ISO
-R9
TPWR1
TPWR0
+
+ +
+
R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
40 MIL trace
20 MIL trace
20MIL
20 MIL trace
20MIL
20 MIL trace
20MIL
LVD/SE Termination for SCSI Channel B
59 85
INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD 1.0
11/18/02
0.1UF
C1669
21
4.7UF
C1745
0.1UF
C1670
21
4.7UF
C1746
0.1UF
C1671
21
4.7UF
C1747
0.1UF
C1388
21
10UF
C1441
3
5
8
10
12
19
21
24
2
4
7
9
11
18
20
23
25
17
22
6
14
16
1
15
13
26
28
27
U98
3
5
8
10
12
19
21
24
2
4
7
9
11
18
20
23
25
17
22
6
14
16
1
15
13
26
28
27
U97
3
5
8
10
12
19
21
24
2
4
7
9
11
18
20
23
25
17
22
6
14
16
1
15
13
26
28
27
U96
R708
20K
R660
4.7K
R662
1K
C1672
0.1UF
CHB_TERMEN53
DIFFSENSEB_R53,57
LVSCDBM13 53,57
LVSCDBPHM 53,57
LVSCDBM1 53,57
LVSCDBM14 53,57
LVSCDBM10 53,57
LVMSGBP53,57
LVCDBP53,57
LVIOBP53,57
LVSCDBP953,57
LVSCDBP1153,57
LVSCDBP1053,57
LVSCDBP853,57
LVREQBP53,57
LVSELBP53,57
LVMSGBM 53,57
LVCDBM 53,57
LVIOBM 53,57
LVSCDBM9 53,57
LVSCDBM11 53,57
LVSCDBM8 53,57
LVREQBM 53,57
LVSELBM 53,57
LVSCDBP453,57
LVSCDBP653,57
LVSCDBPLP53,57
LVACKBP53,57
LVRSTBP53,57
LVBSYBP53,57
LVATNBP53,57
LVSCDBP753,57
LVSCDBP553,57
LVSCDBP1253,57
LVSCDBP1453,57
LVSCDBPHP53,57
LVSCDBP153,57
LVSCDBP353,57
LVSCDBP253,57
LVSCDBP053,57
LVSCDBP1553,57
LVSCDBP1353,57
LVSCDBM4 53,57
LVSCDBM6 53,57
LVSCDBPLM 53,57
LVACKBM 53,57
LVRSTBM 53,57
LVBSYBM 53,57
LVATNBM 53,57
LVSCDBM7 53,57
LVSCDBM5 53,57
LVSCDBM12 53,57
LVSCDBM3 53,57
LVSCDBM2 53,57
LVSCDBM0 53,57
LVSCDBM15 53,57
LVTRMPWR_B55,57