ITP700 Debug Port Design Guide

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8 ITP700 Debug Port Design Guide
Definitions
Term Definition
DPA Debug Port Adapter. Section of ITP hardware that plugs into the target system Debug
Port.
ITP The acronym “ITP” as used within this document refers to an In-Target Probe run-time
control tool as produced by Intel as well as third party vendors. This specification is not
meant to imply that any vendor’s debug tool is preferred over any other.
ITP700 Flex Flex cable adapter to the ITP that connects to a small form factor connector on the target
platform, drastically reducing the footprint and vertical clearance from the standard
ITP700 style debug port. This debug port style currently supports UP configurations only.
JTAG Joint Test Access Group
Local TAP
Master
A device other than the ITP that is designed to control accesses into an IEEE STD 1149
style scan chain and all TAP agents contained within that scan chain. Usually this device
is used for manufacturing test purposes.
LVDPA Low-Voltage Debug Port Adapter. Section of ITP hardware that plugs into the target
system Debug Port that supports operating voltages as low as 0.6V.
TAP IEEE STD 1149 defined test access port
TAP Master A device that is designed to control accesses into an IEEE STD 1149 style scan chain
and all TAP agents contained within that scan chain. The ITP is an example of a TAP
master.
VTERM Termination voltage of the BPM[5:0]# and RESET# signals.
VTAP Pull-up voltage for the ITP scan chain signals