Intel Xeon Processor Multiprocessor Platform Design Guide

95
Methodology for Determining Topology and Routing Guidelines
Equation 9-8. Source Synchronous, Hold Margin
9.1.2 Common Clock
A block diagram of a circuit that was used to develop the basic timing equations is shown in
Figure 9-4.
Figure 9-3. Source Synchronous Timing Diagram for Hold Time
setupskewvbsetupinm
TTTT −−−=
max,min,_arg
(data)
CLK
DATA
DRIVER
STROBE
STROBE
RECEIVER
RECEIVER
STROBE
STROBE
DRIVER
DRIVER
DATARECEIVER
T
setup
T
flight
T
co
(strobe)
T
flight
(strobe)
T
co
(data)
T
margin