Intel Xeon Processor Multiprocessor Platform Design Guide

6
Figures
3-1 Top View - Intel
®
Xeon™ Processor MP Socket Quadrant Layout..................... 19
3-2 Top View - Intel
®
Xeon™ Processor MP with up to 2-MB L3 Cache on the
0.13 Micron Process Socket Quadrant Layout.................................................... 20
4-1 4-Way Processor Server Component Placement Example in a Midrange
SSI Form Factor.................................................................................................. 21
4-2 Twelve Layer Stack-Up for a 4-Way System ...................................................... 22
4-3 4-Way Stack-Up Example ................................................................................... 23
5-1 4-Way Processor BCLK Topology ...................................................................... 26
5-2 Source Shunt Termination .................................................................................. 27
5-3 Agent-to-Agent BCLK Skew................................................................................ 29
5-4 Dielectric Height to Trace Width Diagram ........................................................... 29
6-1 Serpentine Spacing - Diagram of Spacing to Reference Plane Height Ratio ..... 33
6-2 System Bus I/O Decoupling Guidelines for the Processor .................................. 34
6-3 System Bus I/O Decoupling Guidelines for the Chipset...................................... 35
6-4 4-Way Processor System Bus Topology............................................................. 37
6-5 Cross-Sectional View of 3:1 Ratio for Symmetric Stripline (Edge-to-Edge
Trace Spacing vs. Trace to Reference Plane Height) ......................................... 38
6-6 L1 vs. L2 Length Dependencies.......................................................................... 39
6-7 Wired-OR Topology ............................................................................................ 42
6-8 0.025" Via Pad with 50% of Trace over Reference Plane................................... 43
6-9 Topology 1 for 4-Way Configuration ................................................................... 45
6-10 Example Voltage Translator Circuit..................................................................... 45
6-11 Topology 2 for 4-Way Configuration ................................................................... 46
6-12 BR[3:0]# Connection for 4-Way Configuration .................................................... 47
7-1 Retention Mechanism Outline ............................................................................. 52
7-2 Retention Mechanism Placement and Keep-Out Overview ................................ 53
7-3 Retention Mechanism Ground Ring .................................................................... 54
7-4 Spread Spectrum Modulation Profile .................................................................. 56
7-5 Impact of Spread Spectrum Clocking on Radiated Emissions ............................ 57
7-6 Cancellation of H-fields through Inverse Currents .............................................. 57
7-7 Conceptual Processor Ground Frame ................................................................ 59
7-8 EMI Ground Pad Size and Locations .................................................................. 60
8-1 Power Distribution Block Diagram for 4- Way System Motherboard with
Voltage Regulator Modules................................................................................. 66
8-2 Suggested Twelve Layer Stack-Up for Four Processor Systems ....................... 69
8-3 1206 Capacitor Pad and Via Layouts.................................................................. 72
8-4 Connections to Via Patterns................................................................................ 72
8-5 Processor Lump Model Schematic ..................................................................... 74
8-6 Processor Lump Model Drawing ......................................................................... 75
8-7 “Row” Pattern with Voltage Regulator Module .................................................... 76
8-8 “Row” Pattern with Voltage Regulator Module Schematic .................................. 77
8-9 “Square” Pattern with Voltage Regulator Module................................................ 78
8-10 “Square” Pattern with Voltage Regulator Module Schematic.............................. 79
8-11 “Row” Pattern with Voltage Regulator Module .................................................... 81
8-12 “Row” Pattern with Voltage Regulator Module Schematic .................................. 82
8-13 GTLREF .............................................................................................................. 83
8-14 Suggested GTLREF Generation ......................................................................... 85
8-15 Filter Topology .................................................................................................... 86