Intel Xeon Processor Multiprocessor Platform Design Guide

Methodology for Determining Topology and Routing Guidelines

9.2.4 Signal Quality Metrics

The tight timing and low voltage characteristics of the system bus require clean reception of all

signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage

swing will adversely effect system timings. Excessive ringback, and signal non-monotinicity

cannot by tolerated, since these phenomena may inadvertently advance receiver state machines.

Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity,

and can cause device failure if absolute voltage limits are exceeded. Additionally, over/undershoot

can cause timing degradation due to the build up of inter-symbol interference (ISI) effects.

For these reasons, it is important that the designer work to achieve a solution that provides

acceptable signal quality across all systematic variations encountered in volume manufacturing.

This section documents signal quality metrics used to derive topology and routing guidelines.

9.2.4.1 Noise Margin

The receiver buffers are designed to switch at the threshold voltage. Due to several variables such

as processor variations and system noise, the threshold voltage may change. This variation in the

threshold voltage is known as the noise margin. For the processor the noise margin is assumed to

be 100 mV above and 100 mV below the reference voltage, GTLREF.

Signal quality is measured by observing the linearity of the signal as it passes through the transition

region (GTLREF ± 100 mV) and by observing any signal ringing into the noise margin region. The

upper and lower noise margin levels are referred to as V

and V

respectively.

Table 9-1. System Variables to Consider for Sensitivity Analysis

System Variable Impact on Timings and/or Signal Integrity

Trace/stub lengths High

Trace impedance variations High

Buffer impedance variations High

Buffer capacitance variations Moderate

Er variations

Low (variation is usually small for stripline. Higher for

microstrip)

Pattern dependency Low to High (high for long lines)

Ground return path discontinuities Potentially high

Trace to trace spacing High

AC losses Moderate

Receiver capacitance variations High

Package parasitic effects High

Termination resistor variations Low (if high tolerance resistors are used)

Layer to layer Zo and Er variations Moderate

Serpentine spacing Moderate

Simultaneous Switching Outputs (SSO) Moderate

Inter-Symbol Interference (ISI) Moderate