64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 19
—Intel
®
Xeon™ Processor with 800 MHz System Bus
72 XXX Fixed
L-bit of CS and LMA bit of IA32_EFER register may
have erroneous value for one instruction following
mode transition in Hyper-Threading Technology-
Enabled processor supporting Intel® Extended
Memory 64 Technology (Intel® EM64T)
73 XXXX Fixed
The base of an LDT (Local Descriptor Table) register
may be non-zero on a processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
74 X Fixed
Unaligned Page-Directory-Pointer (PDPTR) Base with
32-bit mode PAE (Page Address Extension) paging
may cause processor to hang
75 XXXXXNo Fix
Memory ordering failure may occur with snoop
filtering third-party agents after issuing and
completing a BWIL (Bus Write Invalidate Line) or BLW
(Bus Locked Write) transaction
76 XXXXXNo Fix
Control Register 2 (CR2) can be updated during a REP
MOVS/STOS instruction with fast strings enabled
77 XXXXXNo Fix
REP STOS/MOVS instructions with RCX >= 2^32 may
cause system hang
78 XXXX Fixed
REP MOVS or REP STOS instruction with RCX >=
2^32 may fail to execute to completion or may write
to incorrect memory locations on processors
supporting Intel® Extended Memory 64 Technology
(Intel® EM64T)
79 XXXXX
Plan
Fix
An REP LODSB or an REP LODSD or an REP LODSQ
instruction with RCX >= 2^32 may cause a system
hang on processors supporting Intel® Extended
Memory 64 Technology (Intel® EM64T)
80 XXXX Fixed
Data access which spans both canonical and non-
canonical address space may hang system
81 XXXXX
Plan
Fix
Running in System Management Mode (SMM) and L1
data cache adaptive mode may cause unexpected
system behavior when SMRAM is mapped to
cacheable memory
82 XXXXXNo Fix
A 64-bit value of Linear Instruction Pointer (LIP) may
be reported incorrectly in the Branch Trace Store
(BTS) memory record or in the Precise Event Based
Sampling (PEBS) memory record
83 XXXXX
Plan
Fix
It is possible that two specific invalid opcodes may
cause unexpected memory accesses
84 XXXXXNo Fix
At core-to-bus ratios of 16:1 and above Defer Reply
transactions with non-zero REQb values may cause a
Front Side Bus stall
85 XXXXXNo Fix
Processor may issue Frost Side Bus transactions up to
6 clocks after RESET# is asserted
86 XXXXXNo Fix
Front Side Bus machine checks may be reported as a
result of on-going transactions during warm reset
S87 XXXXXNo Fix
Writing the local vector table (LVT) when an interrupt
is pending may cause an unexpected interrupt
3.2 Errata (Sheet 5 of 6)
No.
D-0/
0F34
h
E-0/
0F41
h
G-1/
0F49
h
N-0/
0F43
h
R-0/
0F4A
h
Plans Errata