Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

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Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide 3

Contents

1 Introduction ................................................................................................................17

1.1 Terminology.........................................................................................................17

1.2 Reference Documentation...................................................................................20

1.3 System Overview ................................................................................................ 21

1.3.1 Intel

Xeon™ Processors...................................................................22

1.3.2 Intel

E7500/E7501 Chipset...............................................................23

1.3.2.1 Intel

E7500/E7501 Memory Controller Hub (MCH) ............24

1.3.2.2 I/O Controller Hub 3 (Intel

ICH3-S).....................................25

1.3.2.3 PCI/PCI-X 64-bit Hub 2 (Intel

82870P2 P64H2) .................25

1.3.3 Peak Bandwidth Summary .................................................................26

1.3.4 System Configurations .......................................................................26

2 Component Quadrant Layout.............................................................................. 27

2.1 Intel

Xeon™ Processor Quadrant Layout .........................................................28

2.2 Intel

E7500/E7501 Chipset MCH Quadrant Layout ..........................................29

2.3 Intel

ICH3-S Quadrant Layout ...........................................................................30

2.4 Intel

82870P2 P64H2 Quadrant Layout ............................................................31

3 Baseboard Requirements .....................................................................................33

3.1 Platform Stack-Up ...............................................................................................33

3.2 Processor Retention Mechanism Placement and Keep-Outs ............................. 34

3.3 Platform Component Placement .........................................................................37

3.4 SSI Compliance................................................................................................... 38

3.4.1 Mounting Hole Placement ..................................................................38

3.4.2 Volume Constraints for Typical General Purpose Baseboards ..........41

3.4.3 Standard Cutout for Onboard I/O Ports..............................................42

3.4.4 Connectors .........................................................................................43

3.4.4.1 Entry SSI Main Power Connector .........................................43

3.4.4.2 +12 Volt Power Connector.................................................... 43

3.4.4.3 Auxiliary Signal Connector....................................................44

3.4.4.4 Cooling Fan Connector.........................................................44

4 Platform Clock Routing Guidelines .................................................................. 45

4.1 HOST_CLK Clock Group ....................................................................................48

4.1.1 HOST_CLK Clock Topology...............................................................48

4.1.2 HOST_CLK General Routing Guidelines ........................................... 51

4.1.3 CK408 vs. CK408B Requirement .......................................................51

4.2 CLK66 Clock Group ............................................................................................52

4.2.1 CLK66 Skew Requirements ...............................................................53

4.3 CLK33_ICH3-S Clock..........................................................................................55

4.4 CLK33 Clock Group ............................................................................................56

4.5 CLK14 Clock Group ............................................................................................58

4.6 USBCLK Clock Group .........................................................................................59

4.7 Clock Driver Decoupling......................................................................................60

4.8 Clock Driver Power Delivery................................................................................61