64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

28 64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update
Errata
U42 A push of ESP that faults may zero the upper 32-bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the
processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum, this
instruction fault may change the contents of RSP. This erratum has not been observed in
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U43 Enhanced halt state (C1E) voltage transition may affect a system's power
management in a HT Technology enabled processor
Problem: In an HT Technology enabled system, the second logical Processor may fail to wake up from
“Wait-for-SIPI” state during a C1E voltage transition.
Implication: This erratum may affect a system's entry into the power management mode offered by the C1E
event for HT Technology enabled platforms.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U44 Enhanced halt state (C1E) may not be entered in a HT Technology enabled
processor
Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on an
HT Technology enabled system; the processor will not enter C1E until the next SIPI wakeup event
for the second logical processor.
Implication: Due to this erratum, the processor will not enter C1E state.
Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to
issuing the first SIPI to the second logical processor.
Status: For the steppings affected, see the Summary Table of Changes.
U45 When the Execute Disable Bit function is enabled a page fault in a
mispredicted branch may result in a page fault exception
Problem: If a page fault in a mispredicted branch occurs in the ITLB, it should not be reported by the
processor. However, if the execute disable bit function is enabled (IA32_EFER.NXE = 1) and there
is a page fault in a mispredicted branch in the ITLB, a page fault exception may occur.
Implication: When this erratum occurs, a page fault exception may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
U46 Execute Disable Bit set with AD assist may cause livelock
Problem: If Execute Disable Bit is set and the resulting page requires the processor to set the A and/or D bit
(Access and/or Dirty bit) in the PTE, then the processor may livelock.
Implication: When this erratum occurs, the processor may livelock resulting in a system hang or operating
system failure.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.