64-bit Intel Xeon Processor MP with 1MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 11
Summary Table of Changes
V = Mobile Intel
®
Celeron
®
processor on .13 micron process in micro-FCPGA package
W= Intel
®
Celeron
®
M processor
X=Intel
®
Pentium
®
M processor on 90 nm process with 2 MB L2 cache
Y=Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AA= Intel
®
Pentium
®
® processor Extreme Edition and Intel
®
Pentium
®
D processor on 65nm
process
AB = Intel
®
Pentium
®
4 processor on 65 nm process
AC = Intel
®
Celeron
®
processor in 478 Pin Package
AD= Intel
®
Celeron
®
D processor on 65nm process
AE = Intel
®
Core
TM
Duo Processor and Intel
®
CoreTM Solo processor on 65nm process
AF = Dual-Core Intel
®
Xeon
®
processor LV
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and other Intel
products do not use this convention.
Errata (Sheet 1 of 4)
No.
A-0/
0F41h
B-0/
0F49H
Plans Errata
J1 X X No Fix Transaction is not retired after BINIT#
J2 X X No Fix Invalid opcode 0FFFh requires A ModRM byte
J3 X X No Fix Processor may hang due to speculative page walks to non-existent system memory
J4 X X No Fix Memory type of the load lock different from its corresponding store unlock
J5 X X No Fix Machine check architecture error reporting and recovery may not work as expected
J6 X X No Fix Debug mechanisms may not function as expected
J7 X X No Fix Cascading of performance counters does not work correctly when forced overflow is
enabled
J8 X X No Fix EMON event counting of x87 loads may not work as expected
J9 X X No Fix System bus interrupt messages without data and which receive a hardfailure response may
hang the processor
J10 X X No Fix The processor signals page fault exception (#PF) instead of alignment check exception
(#AC) on an unlocked CMPXCHG8B instruction
J11 X X No Fix FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions
J12 X X No Fix Processor issues inconsistent transaction size attributes for locked operation
J13 X X No Fix When the processor is in the system management mode (SMM), debug registers may be
fully writeable
J14 X X No Fix Shutdown and IERR# may result due to a machine check exception on a Hyper-Threading
Technology enabled processor
J15 X X No Fix Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle
J16 X X No Fix System may hang if a fatal cache error causes Bus Write Line (BWL) transaction to occur to
the same cache line address as an outstanding Bus Read Line (BRL) or Bus
Read-Invalidate Line (BRIL)
J17 X X No Fix A write to an APIC register sometimes may appear to have not occurred
J18 X X No Fix Parity error in the L1 cache may cause the processor to hang
J19 X X No Fix Sequence of locked operations can cause two threads to receive stale data and cause
application hang
J20 X X No Fix Locks and SMC detection may cause the processor to temporarily hang