64-bit Intel Xeon Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus 15
(1 MB and 2 MB L2 Cache Versions) Specification Update
Summary Table of Changes
S43 XX FixedRecursive page walks may cause a system hang
S44 XFixedWRMSR to bit[0] of IA32_MISC_ENABLE register changes
only one logical processor on a Hyper-Threading Technology
enabled processor
S45 XXXX FixedVERR/VERW instructions may cause #GP fault when
descriptor is in non-canonical space
S46 XFixedINS or REP INS flows save an incorrect memory address for
SMI on processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S47 XFixedFXSAVE instruction may result in incorrect data on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S48 XX FixedThe base of a null segment may be non-zero on a processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S49 XX FixedUpper 32 bits of FS/GS with null base may not get cleared in
Virtual-8086 Mode on processors with Intel® Extended
Memory 64 Technology (Intel® EM64T) Enabled
S50 XXXXXNo FixProcessor may fault when the upper 8 bytes of segment
selector is loaded from a far jump through a call gate via the
Local Descriptor Table
S51 XFixedCompatibility mode STOS instructions may alter RSI register
results on a processor supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
S52 XFixedLDT descriptor which crosses 16 bit boundary access does
not cause a #GP fault on a processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
S53 XFixedUpper reserved bits are incorrectly checked while loading
PDPTR's on a processor supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
S54 XXXXXNo FixLoading a stack segment with a selector that references a
non-canonical address can lead to a #SS fault on a processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
S55 XFixedCPUID instruction incorrectly reports CMPXCH16B as
supported
S56 XXXXXNo FixFXRSTOR may not restore non-canonical effective addresses
on processors with Intel® Extended Memory 64 Technology
(Intel® EM64T) enabled
S57 XXXXXNo FixA push of ESP that faults may zero the upper 32-bits of RSP
S58 XFixedEnhanced halt state (C1E) voltage transition may affect a
system’s power management in a Hyper-Threading
Technology enabled processor
S59 XXXXNo FixEnhanced halt state (C1E) may not be entered in a
Hyper-Threading Technology enabled processor
S60 XFixedWhen the Execute Disable Bit function is enabled a page fault
in a mispredicted branch may result in a page fault exception
S61 XFixedExecute Disable Bit set with AD assist may cause livelock
S62 XX FixedThe Execute Disable Bit fault may be reported before other
types of page fault when both occur
Errata (Sheet 3 of 5)
No.
D-0/
0F34h
E-0/
0F41h
G-1/
0F49h
N-0/
0F43h
R-0/
0F4Ah
Plans Errata