64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 37
—Intel
®
Xeon™ Processor with 800 MHz System Bus
Status: For the steppings affected, see the Summary Table of Changes.
S50 Processor may fault when the upper 8 bytes of segment
selector is loaded from a far jump through a call gate via the
Local Descriptor Table
Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call
gate via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the
upper 8-byte access may wrap and access an incorrect descriptor in the LDT.
This only occurs on an LDT with a LIMIT>0x10008 with a 16-byte descriptor
that has a selector of 0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and
access an incorrect descriptor within the LDT, potentially resulting in a fault or
system hang. Intel has not observed this erratum with any commercially
available software.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S51 Compatibility mode STOS instructions may alter RSI register
results on a processor supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode and executes a
STOS instruction in compatibility mode, it may modify the RSI register
contents.
Implication: When this erratum occurs, systems may encounter unexpected behavior.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S52 LDT descriptor which crosses 16 bit boundary access does not
cause a #GP fault on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T in IA-32e mode accesses an LDT
entry (16-byte) that crosses the 0xffff limit, a #GP fault is not signaled and
instead the upper 8-bytes of the entry is fetched from the wrapped around
address (usually 0x0). This will cause the erroneous data to be loaded into the
upper 8-bytes of the descriptor.
Implication: When this erratum occurs, systems may encounter unexpected behavior. Intel
has not observed this erratum with any commercially available software.
Workaround:Software should prevent LDT selector accesses from crossing the 0xffff limit.
Status: For the steppings affected, see the Summary Table of Changes.
S53 Upper reserved bits are incorrectly checked while loading
PDPTR's on a processor supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
Problem: In IA-32 and IA-32e mode of the Intel processor, upper reserved bits are
incorrectly checked while loading PDPTR's, allowing software to set the
reserved bits.
Implication: Operating system or driver software is able to set the reserved bits which may
result in an unexpected system behavior.