64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
18 Order Number: 302402-024
53 X Fixed
Upper reserved bits are incorrectly checked while
loading PDPTR's on a processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T)
54 XXXXXNo Fix
Loading a stack segment with a selector that
references a non-canonical address can lead to a #SS
fault on a processor supporting Intel® Extended
Memory 64 Technology (Intel® EM64T)
55 X Fixed
CPUID instruction incorrectly reports CMPXCH16B as
supported
56 XXXXXNo Fix
FXRSTOR may not restore non-canonical effective
addresses on processors with Intel® Extended
Memory 64 Technology (Intel® EM64T) enabled
57 XXXXXNo Fix
A push of ESP that faults may zero the upper 32-bits
of RSP
58 X Fixed
Enhanced halt state (C1E) voltage transition may
affect a system’s power management in a Hyper-
Threading Technology enabled processor
59 XXXXNo Fix
Enhanced halt state (C1E) may not be entered in a
Hyper-Threading Technology enabled processor
60 X Fixed
When the Execute Disable Bit function is enabled a
page fault in a mispredicted branch may result in a
page fault exception
61 X Fixed
Execute Disable Bit set with AD assist may cause
livelock
62 XX Fixed
The Execute Disable Bit fault may be reported before
other types of page fault when both occur
63 X Fixed
Writes to IA32_MISC_ENABLE may not update flags
for both logical processors
64 X Fixed
Execute Disable Bit set with CR4.PAE may cause
livelock
65 X Fixed
SYSENTER or SYSEXIT instructions may experience
incorrect canonical address checking on processors
supporting Intel® Extended Memory 64 Technology
(Intel® EM64T)
66 XXXXXNo Fix
Checking of Page Table Base Address may not match
Address Bit Width supported by the platform
67 XXXXXNo Fix
IA32_MCi_STATUS MSR may improperly indicate that
additional MCA information may have been captured
68 XXXXXNo Fix
With Trap Flag (TF) asserted, FP instruction that
triggers unmasked FP Exception may take single step
trap before retirement of instruction
69 XXXXXNo Fix
PDE/PTE loads and continuous locked updates to the
same cache line may cause system livelock
70 X Fixed
MCA-corrected memory hierarchy error counter may
not increment correctly
71 XXXXX
No Fix
Branch Trace Store (BTS) and Precise Event-Based
Sampling (PEBS) may update memory outside the
BTS/PEBS buffer
3.2 Errata (Sheet 4 of 6)
No.
D-0/
0F34
h
E-0/
0F41
h
G-1/
0F49
h
N-0/
0F43
h
R-0/
0F4A
h
Plans Errata