Intel Xeon Processor Specification Update

Intel
®
Xeon
®
Processor Specification Update 39
Errata
• Simultaneously, an event that requires micro-architectural synchronization among the two
logical processors occurs on the second logical processor. This event may cause an invalid
instruction pointer to be stored on the ring 0 stack during the transition to GP fault handler on
the first logical processor.
Implication: The instruction pointer stored on the stack may be invalid, potentially causing errors during
execution of or return from the GP fault handler.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P39 Shutdown and IERR# may result due to a machine check exception on a
Hyper-threading Technology enabled processor
Problem: When a machine check exception (MCE) occurs due to an internal error, both logical processors on
a HT Technology enabled processor normally vector to the MCE handler. However, if one of the
logical processors is in the “Wait-for-SIPI” state, that logical processor will not have an MCE
handler and will shut down and assert IERR#.
Implication: A processor with a logical processor in the “Wait for SIPI” state will shut down when an MCE
occurs on the other thread.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
P40 Hyper-Threading Technology enabled processors may hang in the presence
of extensive self-modifying code
Problem: For multiprocessor platforms, in which HT Technology enabled processors are executing extensive
self modifying code, and branch trace messages are enabled on at least one logical processor, the
system may hang. In this scenario, a processor executing within 1K of code being written to by
another processor may attempt to end this flow, thereby resulting in a hang.
Implication: When this erratum occurs the system will hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
P41 Global bit incorrectly set for secondary logical processors in ITLB
Problem: Due to a boundary condition in the translation look-aside buffer logic, the global bit information in
the TLB entry for a mapping belonging to the first logical processor can overwrite the global bit
information for a mapping belonging to the second logical processor. This occurs in the following
scenario:
• The first logical processor misses the ITLB resulting in a page walk.
• The second logical processor also misses the ITLB and generates a page walk.
Note: In certain timing scenarios within the processor, the leftover global bit information from the first
logical processor may overwrite the second logical processor.
Implication: When this erratum occurs, if the Page global bit for the second logical processor is overwritten with
a 0b, this will result in performance degradation for the first logical processor. If the page global bit
is incorrectly changed from a 0 to 1, this erratum may result in software failures.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.