Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 37
Errata
O62 Incorrect PIROM L3 cache present value
Problem: The L3 Cache Present bit, located at 78:0h in the processor information read only memory
(PIROM), should be programmed to 3Fh - indicating that an L3 cache is present. The L3 cache
present bit value returned is 3Eh, which indicates that the L3 cache is not present. L3 cache size is
not affected by the L3 cache present bit. L3 cache size can be determined by reading the L3 cache
size register located at 29 -2Ah in the PIROM.
Implication: Intel expects the impact of this issue to be limited to incorrect L3 cache identification on BIOS
POST or OS system information screens. L3 cache functionality is not affected by this incorrect
value. However, BIOS developers and system board manufacturers should judge the impact of this
L3 cache issue on their existing platform designs.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Tables of Changes.
O63 Locks and SMC detection may cause the processor to temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor
executes a synchronization loop that includes one or more bus locks and is waiting for release by
the other logical processor. If the releasing logical processor is executing instructions that are
within the detection range of the self modifying code (SMC) logic, then the processor may be
locked in the synchronization loop until the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround: None at this time.
Status: For the steppings affected, see the Summary of Table of Changes.
O64 Incorrect debug exception (#DB) may occur when a data breakpoint is set
on an FP instruction
Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain
data about the FP instruction that is causing the FP event. If a data breakpoint is set on the
instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint
resulting in a Debug Exception.
Implication: An incorrect debug exception (#DB) may occur if data breakpoint is placed on an FP instruction.
Intel has not observed this erratum with any commercially available software or system.
Workaround: None at this time.
Status: For the steppings affected, see the Summary of Table of Changes.
O65 Modified cache line eviction from L2 cache may result in write back of stale
data
Problem: It is possible for a modified cache line to be evicted from the L2 cache just prior to another update
to the same line by software. In rare circumstances, the processor may accrue two bus queue entries
that have the same address but have different data. If an external snoop is generated in a narrow
timing window, the data from the older eviction may be used to respond to the external snoop.
Implication: In the event that this erratum occurs, the contents of memory will be incorrect. This may result in
application, operating system, or system failure
.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Table of Changes.