Intel Xeon Processor LV and ULV Specification Update

Errata
42 Specification Update
Status: For the steppings affected, see the Summary Tables of Changes.
AF77. Performance Monitoring Events for Hardware Prefetch Requests
(4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not be
Accurate
Problem: Performance monitoring events that count hardware prefetch requests and prefetch
misses may not be accurate.
Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and
Hardware Prefetch Request Cache Misses.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF78. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
Problem: When the processor is going into shutdown due to an RSM inconsistency failure,
EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be
asserted. This may be observed if the processor is taken out of shutdown by NMI#.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF79. Store Ordering May be Incorrect between WC and WP Memory Types
Problem: According to Intel
®
64 and IA-32 Intel Architecture Software Developer's Manual,
Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain
the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type
stores do. Due to this erratum, WP stores may not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF80. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
Problem: Under certain conditions, as described in the Software Developers Manual section
"Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors", the processor may perform REP MOVS or REP STOS as write combining
stores (referred to as ―fast strings‖) for optimal performance. FXSAVE may also be
internally implemented using write combining stores. Due to this erratum, stores of a
WB (write back) memory type to a cache line previously written by a preceding fast
string/FXSAVE instruction may be observed before string/FXSAVE stores.