Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

R
D
C
B
B
D
C
1
12345678
2345678
A
A
LAST REVISED:
DRAWN BY:
1900 Prairie City Road
Folsom, California 095630 OF
TITLE:
PROJECT:
Rev:
KC533
Intel Corporation
+V5_0
+V3_3
+V3_3
+V3_3
+V3_3
2N3904_DUAL
+V3_3
74HC682
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0
P1
P2
P3
P4
P5
P6
P7
VCC
P_GR_Q_N
P_EQ_Q_N
74LVC00
74LVC00
+V3_3
+V3_3
+V3_3
74LVC00
74LVC00
74LVC00
+V3_3
2N3904_DUAL
74LVC00
CPU Load Line Circuitry & VID Manual Override(Debug Only)
Foster Processor Detection Circuitry
VRD Enable logic
8574
VRD_VID0
VRD_VID4
VRD_VID3
VRD_VID2
VRD_VID1
VRD_VID3
72
VRD_VID[4:0]
CPU0_VID0
CPU0_VID4
6,74
CPU0_VID[4:0]
CPU0_VID3
CPU0_VID2
CPU0_VID1
11
13
12
14
7
U75
R1031
1K
VRD_OFF_N
VRD_OFF_N
72
CPU1_VID4
4,74
CPU1_VID[4:0]
CPU1_VID3
CPU1_VID2
CPU1_VID1
CPU1_VID0
R1030
10K
NO POP
1K
R1029
14
25
63
Q53
DP_MODE
7,72
11
13
12
14
7
U74
6
5
4
14
7
U74
8
10
9
14
7
U74
3
2
1
14
7
U74
3
2
1
14
7
U75
R1056
0
1
2
3
4 5
6
7
8
RP273
0
1K
R1057
8
7
6
54
3
2
1
1K
RP274
PS_PWROK
79,80,82
10
3
5
7
9
12
14
16
18
2
4
6
8
11
13
15
17
20
1
19
U32
CPU0_VID4
CPU0_VID3
CPU0_VID2
CPU0_VID1
CPU0_VID0
CPU0_VID[4:0]
6,74
CPU0_BSEL1
7
CPU0_BSEL0
7,80
CPU1_BSEL0
5,80
CPU1_BSEL1
5
CPU1_VID4
CPU1_VID3
CPU1_VID2
CPU1_VID1
CPU1_VID0
CPU1_VID[4:0]
4,74
THERM_EN
7
VRD_ON_N_R
R1060
1K
CPU_OK
CPU_OK_N_R
3 6
5 2
4 1
Q60
CPU_OK_N
C1707
0.1UF
R1021
10K
10K
R1022
VRD_ON_N
VID_OK
VID_MATCH_N
FOSTER_OCC_N
1.0INTEL (R) E7501 CHIPSET CUSTOMER REFERENCE BOARD
11/18/02