Intel Xeon Processor 2.80 GHz Specification Update

Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update 19
Errata
behavior for a single processor to have a BWL and a BRL/BRIL concurrently outstanding to the
same address, this may represent an unexpected scenario to system logic within the chipset.
Implication: The processor may not be able to fully execute the machine check handler in response to the fatal
cache error if system logic does not ensure forward progress on the System Bus under this scenario.
Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery
from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL
transactions is not important. Forward progress is the primary requirement.
Status: For the steppings affected, see the Summary Table of Changes.
D17. A write to APIC task priority register (TPR) that lowers priority may seem to
have not occurred
Problem: Uncacheable stores to the APIC space are handled in a non-synchronous way with respect to the
speed at which instructions are retired. If an instruction that masks the interrupt flag e.g. CLI is
executed soon after an uncacheable write to the TPR that lowers the APIC priority the interrupt
masking operation may take effect before the actual priority has been lowered. This may cause
interrupts whose priority is lower than the initial TPR but higher than the final TPR to not be
serviced until the interrupt flag is finally cleared e.g. STI. Interrupts will remain pended and are not
lost.
Implication: This condition may allow interrupts to be accepted by the processor but may delay their service
Workaround: This can be avoided by issuing a TPR Read after a TPR Write that lowers the TPR value. This will
force the store to the APIC priority resolution logic before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
D18. Parity error in the L1 cache may cause the processor to hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D19. Locks and SMC detection may cause the processor to temporarily hang
Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor
executes a synchronization loop that includes one or more bus locks and is waiting for release by
the other logical processor. If the releasing logical processor is executing instructions that are
within the detection range of the self modifying code (SMC) logic, then the processor may be
locked in the synchronization loop until the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D20. Incorrect debug exception (#DB) may occur when a data breakpoint is set
on an FP instruction
Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain
data about the FP instruction that are causing the FP event. If a data breakpoint is set on the