64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
26 Order Number: 302402-024
Status: For the steppings affected, see the Summary Table of Changes.
S7 Cascading of performance counters does not work correctly
when forced overflow is enabled
Problem: The performance counters are organized into pairs. When the CASCADE bit of
the Counter Configuration Control Register (CCCR) is set, a counter that
overflows will continue to count in the other counter of the pair. The
FORCE_OVF bit forces the counters to overflow on every non-zero increment.
When the FORCE_OVF bit is set, the counter overflow bit will be set but the
counter no longer cascades.
Implication: The performance counters do not cascade when the FORCE_OVF bit is set.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S8 EMON event counting of x87 loads may not work as expected
Problem: If a performance counter is set to count x87 loads and floating-point
exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become
corrupted.
Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become
corrupted.
Workaround:This erratum will not occur with floating point exceptions masked. If floating-
point exceptions are unmasked, then performance counting of x87 loads
should be disabled.
Status: For the steppings affected, see the Summary Table of Changes.
S9 System bus interrupt messages without data and which receive
a hard-failure response may hang the processor
Problem: When a system bus agent (processor or chipset) issues an interrupt
transaction without data onto the system bus, and the transaction receives a
hard-failure response, a potential processor hang can occur. The processor,
which generates an inter-processor interrupt (IPI) that receives hard-failure
response, will still log the MCA error event cause as hard-failure, even if the
APIC causes a hang. Other processors, which are true targets of the IPI, will
also hang on hard failure-without-data, but will not record an MCA hard-failure
event as a cause. If a hard-failure response occurs on a system bus interrupt
message with data, the APIC will complete the operation so as not to hang the
processor.
Implication: The processor may hang.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S10 The processor signals page fault exception (#PF) instead of
alignment check exception (#AC) on an unlocked CMPXCHG8B
instruction
Problem: If a page fault exception (#PF) and alignment check exception (#AC) both
occur for an unlocked CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on the #AC before the #PF will be affected since #PF is
signaled in this case.