64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
16 Order Number: 302402-024
15 XXXXXNo Fix
Processor may hang under certain frequencies and
12.5% STPCLK# duty cycle
16 XXXXXNo Fix
System may hang if a fatal cache error causes bus
write line (BWL) transaction to occur to the same
cache line address as an outstanding bus read line
(BRL) or bus read-invalidate line (BRIL)
17 XXXXXNo Fix
A write to APIC task priority register (TPR) that lowers
priority may seem to have not occurred
18 XXXXXNo Fix
Parity error in the L1 cache may cause the processor
to hang
19 XX Fixed
Sequence of locked operations can cause two threads
to receive stale data and cause application hang
20 X Fixed
A 16-bit address wrap resulting from a near branch
(jump or call) may cause an incorrect address to be
reported to the #GP exception handler
21 XXXXXNo Fix
Bus locks and SMC detection may cause the processor
to temporarily hang
22 Fixed
Incorrect physical address size returned by CPUID
instruction
23 XXXXXNo Fix
Incorrect debug exception (#DB) may occur when a
data breakpoint is set on an FP instruction
24 XXXXXNo Fix xAPIC may not report some illegal vector errors
25 XXXXX
Plan
Fix
Enabling no-eviction mode (NEM) may prevent the
operation of the second logical processor in a Hyper-
Threading Technology enabled boot strap processor
(BSP)
26 XXXXX
Plan
Fix
TPR (Task Priority Register) updates during voltage
transitions of power management events may cause a
system hang
27 XXXXNo Fix
Interactions between the instruction translation
lookaside buffer (ITLB) and the instruction streaming
buffer may cause unpredictable software behavior
28 XXX Fixed
STPCLK# signal assertion under certain conditions
may cause a system hang
29 XXXXXNo Fix
Incorrect duty cycle is chosen when on-demand clock
modulation is enabled in a processor supporting
Hyper-Threading Technology
30 XXXXXNo Fix
Memory aliasing of pages as uncacheable memory
type and write back (WB) may hang the system
31 XXXXXNo Fix
Using STPCLK# and executing code from very slow
memory could lead to a system hang
32 XXXXXNo Fix
Processor provides a 4-byte store unlock after an 8-
byte load lock
33 Duplicate Erratum: see S5
34
XXXXX
Plan
Fix
Execution of IRET and INTn instructions may cause
unexpected system behavior
3.2 Errata (Sheet 2 of 6)
No.
D-0/
0F34
h
E-0/
0F41
h
G-1/
0F49
h
N-0/
0F43
h
R-0/
0F4A
h
Plans Errata