Intel Xeon Processor LV and ULV Specification Update

Errata
Specification Update 39
Workaround:
Status: For the steppings affected, see the Summary Tables of Changes.
AF66. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Problem: PDR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit
8) of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of
the following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF67. An Asynchronous MCE During a Far Transfer May Corrupt ESP
Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR
RET or IRET and in the presence of certain internal conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a
triple fault will occur due to the corrupted stack pointer, resulting in a processor
shutdown. If the MCE is called with a stack switch, e.g. when the CPL (Current
Privilege Level) was changed or when going through an interrupt task gate, then the
corrupted ESP will be saved on the new stack or in the TSS (Task State Segment), and
will not be used.
Workaround: Use an interrupt task gate for the machine check handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AF68. BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts
Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software
interrupt may result in the overwriting of BTM/BTS branch-from instruction address by
the LBR (Last Branch Record) branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AF69. Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get