Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Memory Interface Routing Guidelines
94 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
6.7 DC Biasing Signals
The DC Biasing signals are DDR signals which are not channel configuration specific. Table 6-9
documents all of these signals, indicating the new names for many of these signals. Many of the
E7501 chipset MCH usages have been changed from the original E7500 chipset MCH
recommendation. This section documents a compatibility layout for both E7500 chipset MCH and
E7501 chipset MCH with stuffing options, dependant on which MCH is used.
Table 6-9. DC Biasing Ball Differences Between Intel
®
E7500 Chipset MCH and Intel
®
E7501
Chipset MCH
Ball Intel
®
E7500 Chipset MCH Intel
®
E7501 Chipset MCH
AM22 RCVENIN_A# No Connect
N30 RCVENIN_B# No Connect
AG20 RCVENOUT_A# RCVEN_A
R25 RCVENOUT_B# RCVEN_B
AK17 DDRCVOH_A DDRCVO_A
W32 DDRCVOH_B DDRCVO_B
AN16 DDRCVOL_A No Connect
V29 DDRCVOL_B No Connect
AH17 DDRCOMP_A DDRCOMP_A
W30 DDRCOMP_B DDRCOMP_B
AK21,AM16,
AL9,AJ7
DDRVREF_A[3:0] DDRVREF_A[3:0]
AK27 DDRVREF_A4 Reserved
AJ28 DDRVREF_A5 ODTCOMP
N33,U26,
AG32,AC25
DDRVREF_B[3:0] DDRVREF_B[3:0]
E30,M25 DDRVREF_B[5:4] Reserved