Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide 187
Platform Power Delivery Guidelines
Figure 11-11. Power-Up Sequencing
Figure 11-12. Power-Down Sequencing
95% of 3.3 V
> T
O
+ 100 ms
> 10 ms
1 ms < T < 10 ms
Pr o c e s s or PW RGOOD
Processor RESET#
VRx PWRGD
BSEL[1:0]
VID[4:0]
PWR_OK / OUTEN
3.3 V
T
0
+ 1 mS
T
0
3.3 V
PWROK
95% 3.3 v olt lev el
Power D own W arning > 1 ms