64-bit Intel Xeon Processor MP with up to 8MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 35
Errata
U71. Writing the Local Vector Table (LVT) when an interrupt is pending may
cause an unexpected interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new
interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even
if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for
that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for
the vector will be left set in the in-service register and mask all interrupts at the same or lower
priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector
was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts
that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore
the spurious vector should not be used when writing the LVT.
Status: For the steppings affected, see the Summary Table of Changes.
U72. The processor may issue multiple code fetches to the same cache line for
systems with slow memory
Problem: Systems with long latencies on returning code fetch data from memory, for example BIOS ROM,
may cause the processor to issue multiple fetches to the same cache line, once per each instruction
executed.
Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this
erratum, in a commercially available system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U73. Starting BCLK prior to VCC being stable may cause start up problems with
PLL
Problem: The PLL (Phase Lock Loop) may attempt to lock inappropriately if BCLK (Bus Clock) is started
prior to VCC being stable.
Implication: The processor may fail to boot due to this erratum.
Workaround: BCLK needs to be inactive until VCC is stable.
Status: For the steppings affected, see the Summary Table of Changes.
U74. IRET under certain conditions may cause an unexpected Alignment Check
Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction
even though alignment checks were disabled at the start of the IRET. This can only occur if the
IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not
affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the
interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary
before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment
checks are disabled at the start of the IRET. This erratum can only be observed with a software
generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Table of Changes.