Intel Xeon Processor MP Specification Update

40 Intel
®
Xeon
®
Processor MP Specification Update
Errata
O74 With Trap Flag (TF) asserted, FP instruction that triggers an unmasked FP
exception may take single step trap before retirement of instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for
external events to occur, including a transition to a lower power state. When resuming from the
lower power state, it may be possible to take the single step trap before the execution of the original
FP instruction completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
O75 PDE/PTE loads and continuous locked updates to the same cache line may
cause a system livelock
Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates to a cache
line that is being accessed by another processor doing a page table walk, the page table walk may
not complete.
Implication: Due to this erratum, the system may livelock until some external event interrupts the locked
update. Intel has not observed this erratum with any commercially available software.
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
O76 Branch Trace Store (BTS) and Precise Event Based Sampling (PEBS) may
update memory outside the BTS/PREBS buffer
Problem: If the BTS/PREBS buffer is defined such that:
• The difference between BTS/PREBS buffer base and BTS/PREBS absolute maximum is not
an integer multiple of the corresponding record sizes.
• BTS/PREBS absolute maximum is less than a record size from the end of the virtual address
space.
• The record that would cross BTS/PREBS absolute maximum will also continue past the end of
the virtual address space.
A BTS/PREBS record can be written that will wrap at the 4G boundary (IA-32) or 2^64 boundary
(Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) mode), and write memory outside of the
BTS/PREBS buffer.
Implication: Software that uses BTS/PREBS near the 4G boundary (IA-32) or 2^64 boundary (Intel EM64T
mode), and defines the buffer such that it does not hold an integer multiple of records can update
memory outside the BTS/PREBS buffer.
Workaround: Define BTS/PREBS buffer such that BTS/PREBS absolute maximum minus BTS/PREBS buffer
base is integer multiple of the corresponding record sizes as recommended in the IA-32 Intel
®
Architecture Software Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
O77 Memory Ordering Failure may occur with Snoop Filtering Third-Party
Agents after issuing and completing a BWIL (Bus Write Invalidate Line) or
BLW (Bus Locked Write) transaction
Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW
transaction, retain data from the addressed cache line in shared state even though the specification