Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 29
Errata
O30 When the processor is in the system management mode (SMM), debug
registers may be fully writeable
Problem: When in system management mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the
processor should block writes to the reserved bit locations. Due to this erratum, the processor may
not block these writes. This may result in invalid data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values
in the reserved bits are maintained.
Status: For the steppings effected, see the Summary Table of Changes.
O31 Associated counting logic must be configured when using event selection
control (ESCR) MSR
Problem: ESCR MSRs allow software to select specific events to be counted, with each ESCR usually
associated with a pair of performance counters. ESCRs may also be used to qualify the detection of
at-retirement events that support precise-event-based sampling (PEBS). A number of performance
metrics that support PEBS require a 2
nd
ESCR to tag uops for the qualification of at-retirement
events. (The first ESCR is required to program the at-retirement event.) Counting is enabled via
counter configuration control registers (CCCR) while the event count is read from one of the
associated counters. When counting logic is configured for the subset of at-retirement events that
require a 2
nd
ESCR to tag uops, at least one of the CCCRs in the same group of the 2
nd
ESCR must
be enabled.
Implication: If no CCCR/counter is enabled in a given group, the ESCR in that group that is programmed for
tagging uops will have no effect. Hence a subset of performance metrics that require a 2
nd
ESCR
for tagging uops may result in 0 count.
Workaround: Ensure that at least one CCCR/counter in the same group as the tagging ESCR is enabled for those
performance metrics that require two ESCRs and tagging uops for at-retirement counting.
Status: For the steppings effected, see the Summary Table of Changes.
O32 Livelock may occur when bus parking is disabled
Problem: A livelock may occur when processor bus parking is disabled, and when (1) the processor is the
symmetric owner of the bus with one internal request pending, and (2) the processor observes the
assertion of BPRI#, BNR# or a full IOQ. In this scenario, the processor bus interface unit assumes
that the assertion of ADS# is not required, deasserts BREQ, and, as a result, relinquishes bus
ownership without issuing the pending request. If the BPRI#, BNR# or full IOQ pattern continues
coincident with the arbitration phase of the processor that still has only one outstanding internal
request, livelock may occur. Assertion of bus parking, any change to the regular pattern of BPRI#
or BNR# assertion noted above, or the arrival of a second internal transaction will release the
processor from the livelock condition.
Implication: This erratum may result in a livelock.
Workaround: This erratum can be avoided by enabling bus parking. The deassertion of signal A15# during the
active-to-inactive edge of RESET# will enable bus parking.
Status: For the steppings effected, see the Summary Table of Changes.
O33 CPUID function 2 may return incorrect cache size information
Problem: When a HT Technology-enabled processor executes a CPUID instruction with function 2 (02 in the
EAX register), the processor may return incorrect/invalid cache descriptors in the EDX register.
Code must be executing on both logical processors to encounter this erratum.
Implication: When this erratum occurs the data returned to the EDX register may be inaccurate/invalid.