Intel Xeon Processor MP Specification Update

Intel
®
Xeon
®
Processor MP Specification Update 25
Errata
O15 EMON event counting of x87 loads may not work as expected
Problem: If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the
FPU Operand (Data) Pointer (FDP) may become corrupted.
Implication: When this erratum occurs, the FDP may become corrupted.
Workaround: This erratum will not occur with floating-point exceptions masked. If floating-point exceptions are
unmasked, then performance counting of x87 loads should be disabled.
Status: For the steppings effected, see the Summary Table of Changes.
O16 Simultaneous code breakpoint and uncorrectable error results in a
processor hang
Problem: If an instruction fetch results in an uncorrectable error and there is also a debug breakpoint at this
address, the processor will hang and the uncorrectable error will not be logged in the Machine
Check registers.
Implication: When this erratum occurs the processor will livelock.
Workaround: None at this time.
Status: For the steppings effected, see the Summary Table of Changes.
O17 Software controlled clock modulation using a 12.5% or 25% duty cycle may
cause the processor to hang
Problem: Processor clock modulation may be controlled via a processor register
(IA32_THERM_CONTROL). The On-Demand Clock Modulation Duty Cycle is controlled by bits
3:1. If these bits are set to a duty cycle of 12.5% or 25%, the processor may hang while attempting
to execute a floating-point instruction. In this failure, the last instruction pointer (LIP) is pointing to
a floating-point instruction whose instruction bytes are in UC space and which takes a
floating-point error exception. The processor continuously cycles attempting to fetch the bytes of
the faulting floating-point instruction and those following it. This erratum is caused by interactions
between the thermal control circuit and floating-point event handler.
Implication: When software controlled clock modulation is used with a duty cycle of 12.5% or 25% the
processor will go into a sleep state from which it fails to return.
Workaround: Use a duty cycle other than 12.5% or 25%.
Status: For the steppings effected, see the Summary Table of Changes.
O18 Processor samples bus frequency power-on configuration pins at the
assertion of PWRGOOD
Problem: According to the Intel
®
Xeon™ Processor MP Electrical, Mechanical, and Thermal Specifications
(EMTS), the bus frequency-to-core ratio may be set by the power-on configuration option pins
LINT[1:0], IGNNE#, and A20M#. The processor should only sample these pins on the
active-to-inactive transition of RESET#, however, the processor is also sampling these pins on the
inactive-to-active transition of PWRGOOD. The internal initialization done by the processor
between the assertion of PWRGOOD and the deassertion of RESET# may be affected if this ratio
represents a high frequency at which the part will not properly function. This failure to initialize the
processor properly may prevent the processor from coming out of reset or prevent some features
such as the thermal control circuit from working properly.
Implication: The processor may fail to initialize properly if the frequency specified by the power-on
configuration bits sampled at the assertion of PWRGOOD is too high for the processor to function
correctly. On production parts and qualification samples, the frequency is internally limited so that
this erratum should have no impact.
Workaround: No workaround is required for systems using qualification or production processors.