64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

Intel
®
Xeon™ Processor with 800 MHz System Bus—
64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
Specification Update August 2009
42 Order Number: 302402-024
Status: For the steppings affected, see the Summary Table of Changes.
S71 Branch Trace Store (BTS) and Precise Event-Based Sampling
(PEBS) may update memory outside the BTS/PEBS buffer
Problem: If the BTS/PEBS buffer is defined such that:
1.The difference between the BTS/PEBS buffer base and the BTS/PEBS
absolute maximum is not an integer multiple of the corresponding record
sizes,
2.The BTS/PEBS absolute maximum is less than a record size from the end of
the virtual address space, and
3.The record that would cross the BTS/PEBS absolute maximum will also
continue past the end of the virtual address space,
a.BTS/PEBS record can be written that will wrap at the 4-Gbyte boundary
(IA-32) or 2^64 boundary (Intel EM64T mode), and write memory outside
of the BTS/PEBS buffer.
Implication: Software that uses BTS/PEBS near the 4-Gbyte boundary (IA-32) or 2^64
boundary (Intel EM64T mode), and defines the buffer such that it does not
hold an integer multiple of records, can update memory outside the BTS/PEBS
buffer.
Workaround:Define the BTS/PEBS buffer such that the BTS/PEBS absolute maximum minus
the BTS/PEBS buffer base is an integer multiple of the corresponding record
sizes as recommended in the IA-32 IA-32 Intel
®
Architecture Software
Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
S72 L-bit of CS and LMA bit of IA32_EFER register may have
erroneous value for one instruction following mode transition in
Hyper-Threading Technology-Enabled processor supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In an Intel EM64T-enabled processor, the L-bit of the Code Segment (CS)
descriptor may not update with the correct value in a processor with HT
Technology. This may occur in a small window when one logical processor is
making a transition from a compatibility-mode to a 64-bit mode (or vice versa)
while the other logical processor is being stalled. A similar problem may occur
for the observation of the EFER.LMA bit by the decode logic.
Implication: The first instruction following a mode transition may be decoded as if it was
still in the previous mode. For example, this may result in an incorrect stack
size used for a stack operation, i.e. a write of only 4 bytes and an adjustment
to ESP of only 4 in 64-bit mode. The problem can manifest itself on any
instruction which may behave differently in 64-bit mode than in compatibility
mode.
Workaround:It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.