64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 35
—Intel
®
Xeon™ Processor with 800 MHz System Bus
S41 Writing the Echo TPR disable bit in IA32_MISC_ENABLE may
cause a #GP fault
Problem: Writing a ‘1’ to the Echo TPR disable bit (bit 23) in IA32_MISC_ENABLE may
incorrectly cause a #GP fault.
Implication: A #GP fault may occur if the bit is set to a ‘1’.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S42 Incorrect access controls to MSR_LASTBRANCH_0_FROM_LIP
MSR registers
Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register,
an expected #GP fault may not happen.
Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a
#GP fault.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S43 Recursive page walks may cause a system hang
Problem: A page walk, accessing the same page table entry multiple times but at
different levels of the page table, which causes the page table entry to have
its Access bit set may result in a system hang.
Implication: When this erratum occurs, the system may experience a hang.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S44 WRMSR to bit[0] of IA32_MISC_ENABLE register changes only
one logical processor on a Hyper-Threading Technology enabled
processor
Problem: On an HT Technology enabled processor, a write to the fast-strings feature
bit[0] of IA32_MISC_ENABLE register changes the setting for the current
logical processor only.
Implication: Due to this erratum, the non-current logical processor may not update fast-
strings feature bit[0] of IA32_MISC_ENABLE register.
Workaround:BIOS may set the fast-strings enable bit on both logical processors to
workaround this erratum. It is possible for the BIOS to contain a workaround
for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S45 VERR/VERW instructions may cause #GP fault when descriptor
is in non-canonical space
Problem: If a descriptor referenced by the selector specified for the VERR or VERW
instructions is in non-canonical space, it may incorrectly cause a #GP fault on
a processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T).