64-bit Intel Xeon Processor with 800 MHz System Bus (1MB and 2MB L2 Cache Versions) Specification Update

64-bit Intel
®
Xeon
®
Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
August 2009 Specification Update
Order Number: 302402-024 33
—Intel
®
Xeon™ Processor with 800 MHz System Bus
S32 Processor provides a 4-byte store unlock after an 8-byte load
lock
Problem: When the processor is in the Page Address Extension (PAE) mode and detects
the need to set the Access and/or Dirty bits in the page directory or page table
entries, the processor sends an 8 byte load lock onto the system bus. A
subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock
occurs. Correct data is provided since only the lower bytes change, however
external logic monitoring the data transfer may be expecting an 8 byte load
lock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S33 Duplicate erratum: see Erratum S5
S34 Execution of IRET and INTn instructions may cause unexpected
system behavior
Problem: There is a small window of time, requiring alignment of many internal micro
architectural events, during which the speculative execution of the IRET or
INTn instructions in protected or IA-32e mode may result in unexpected
software or system behavior.
Implication: This erratum may result in unexpected instruction execution, events,
interrupts or a system hang when the IRET instruction is executed. The
execution of the INTn instruction may cause debug breakpoints to be missed.
Workaround:It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S35 Data breakpoints on the high half of a floating-point line split
may not be captured
Problem: When a floating point load which splits a 64-byte cache line gets a floating
point stack fault, and a data breakpoint register maps to the high line of the
floating point load, internal boundary conditions exist that may prevent the
data breakpoint from being captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S36 Machine Check Exceptions may not update Last-Exception
Record MSRs (LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine
Check Exceptions occur.
Implication: When this erratum occurs, the LER may not contain information relating to the
machine check exception. They will contain information relating to the
exception prior to the machine check exception.
Workaround:None at this time.
Status: For the steppings affected, see the Summary Table of Changes.