Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Memory Interface Routing Guidelines
86 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
6.1.1 DDR Channel Impedance Requirements
The DDR channel requires different widths for different signals depending on the configuration
used. Table 6-2 indicates the impedances for the trace widths used for routing the data bus.
NOTE: Traces on layers 4 and 5 must be routed orthogonally to each other to minimize the effects of crosstalk.
Table 6-2. Trace Width to impedance Requirements
Trace Width Nominal Trace Impedance (Z
0
)
4 mil 55 Ω ± 10%
5 mil 50
Ω ± 10%
6 mil 45
Ω ± 10%
7.5 mil 40
Ω ± 10%
Figure 6-5. Trace Width and Spacing for All DDR Signals Except CMDCLK_x[3:0]/
CMDCLK_x[3:0]#
Core 5.2 mil
Dielectric 9.6 mil
2.1 mil (1 oz + plating)
Power
Dielectric
Power
Dielectric
Ground
Main Core
Dielectric
Core
Ground
Dielectric
Core
1.4 mil (1 oz)
2.1 mil (1 oz + plating)
Core 5.2 mil
Dielectric 4.3 mil
Core 14.0 mil
Dielectric 9.6 mil
Dielectric 4.3 mil
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Signal Signal Signal
SignalSignal
SignalSignal
SignalSignal
Trace
Width
1.4 mil (1 oz)
1.4 mil (1 oz)
Signal
Signal 1.4 mil (1 oz)
1.4 mil (1 oz)
1.4 mil (1 oz)
Signal
Trace
Spacing
Trace
Spacing
Trace
Width
Trace
Width