Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

4 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
5 System Bus Routing Guidelines........................................................................ 63
5.1 Routing Guidelines for the AGTL+ Source Synchronous 2X and 4X Groups ..... 65
5.2 Routing Guidelines for Common Clock Signals .................................................. 66
5.2.1 Wired-OR Signals............................................................................... 66
5.2.2 RESET# Topology.............................................................................. 66
5.2.3 BR[3:0]# Routing Guidelines .............................................................. 67
5.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals ........... 68
5.3.1 Power Good ....................................................................................... 69
5.3.2 Asynchronous GTL+ Signals Driven by the Processor ...................... 69
5.3.2.1 Proper THERMTRIP# Usage ............................................... 70
5.3.3 System Bus COMP Routing Guidelines ............................................. 70
5.3.4 ODTEN Signal Routing Guidelines .................................................... 70
5.3.5 TESTHI[6:0] Routing Guidelines ........................................................ 71
5.3.6 Asynchronous GTL+ Signals Driven by the Chipset .......................... 71
5.3.6.1 Voltage Translation for INIT#................................................ 72
5.4 Intel
®
Xeon™ Processor with 533 MHz System Bus and Intel
®
Xeon™
Processor with 512-KB L2 Cache ....................................................................... 73
5.4.1 Intel
®
Xeon™ Processor with 533 MHz System Bus Identification .... 73
5.4.2 mPGA604 Socket............................................................................... 73
5.5 SMBus Implementation ....................................................................................... 74
5.5.1 Intel
®
Xeon™ Processor with 512-KB L2 Cache SMBus Signals ...... 74
5.5.2 Thermal Diode and SMBus Interface ................................................. 74
5.5.2.1 Hardware Selection of SMBus Thermal Devices.................. 75
5.5.2.2 Firmware Selection of SMBus Thermal Devices .................. 78
5.5.3 Thermal Sensor Selection .................................................................. 79
5.5.4 Thermal Sensor Layout and Routing Considerations......................... 79
5.5.5 Alternative Method to Obtain PIROM Data ........................................ 80
5.6 Boot Critical Signals ............................................................................................ 80
5.6.1 VID[4:0] .............................................................................................. 80
5.6.2 SKTOCC# Signal Routing Guidelines ................................................ 81
5.6.3 BSEL[1:0] Implementation.................................................................. 81
5.6.4 Sample Implementation Circuit .......................................................... 81
6 Memory Interface Routing Guidelines............................................................. 83
6.1 DDR Overview .................................................................................................... 84
6.1.1 DDR Channel Impedance Requirements ........................................... 86
6.2 Source Synchronous Signal Group Routing ....................................................... 87
6.3 Command Clock Routing .................................................................................... 89
6.4 Source Clocked Signal Group Routing ............................................................... 91
6.5 Chip Select Routing ............................................................................................ 92
6.6 Clock Enable Routing.......................................................................................... 93
6.7 DC Biasing Signals ............................................................................................. 94
6.7.1 Receive Enable Signal ....................................................................... 95
6.7.2 DDR Comp ......................................................................................... 96
6.7.3 DDRVREF and ODTCOMP................................................................ 97
6.7.4 DDRCVO............................................................................................ 99
6.8 DDR Signal Termination and Decoupling ......................................................... 100
6.9 2.5 V Decoupling Requirements ....................................................................... 101