64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 25
Errata
U29 Processor provides a 4-byte store unlock after an 8-byte load lock
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8 byte load lock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U30 Data breakpoints on the high half of a floating-point line split may not be
captured
Problem: When a FP load which splits a 64-byte cache line gets a FP stack fault, and a data breakpoint
register maps to the high line of the FP load, internal boundary conditions exist that may prevent
the data breakpoint from being captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U31 Machine check exceptions may not update Last-Exception Record MSRs
(LERs)
Problem: The Last-Exception Record MSRs (LERs) may not get updated when MCE occur.
Implication: When this erratum occurs, the LER may not contain information relating to the MCE. They will
contain information relating to the exception prior to the MCE.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U32 MOV CR3 performs incorrect reserved bit checking when in PAE paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented
address bits. This checking range should match the address width reported by CPUID instruction
0x8000008. This erratum applies whenever PAE is enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.
This erratum has not been observed with commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U33 Stores to page tables may not be visible to page walks for subsequent loads
without serializing or invalidating the page table entry
Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger
memory access may not get data from a programmatically older store to the page table entry if
there is not a fencing operation or page translation invalidate operation between the store and the
younger memory access. Refer to the IA-32 Intel® Architecture Software Developer’s Manual,
Volume 3B: System Programming Guide for the correct way to update page tables. Software that
conforms to the Software Developer's Manual will operate correctly.
Implication: If the guidelines in the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3B:
System Programming Guide are not followed, stale data may be loaded into the processor's