Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

12 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
11-16 Decoupling Example for a Microstrip Baseboard Design.................................. 192
11-17 GTLREF Divider................................................................................................ 193
11-18 Suggested GTLREF Generation ....................................................................... 194
11-19 MCH Decoupling (Backside View) .................................................................... 196
11-20 Filter Topology for VCCA1_2 (DDR Interface) .................................................. 197
11-21 Filter Topology for VCCAHI1_2 (HUB Interface)............................................... 197
11-22 Filter Topology for VCCACPU_1.2 (System Bus) ............................................. 197
11-23 Power Sequencing Requirement ...................................................................... 198
11-24 Sample 2.5 V Output Enable Control Logic ...................................................... 198
11-25 Example 1.8 V/3.3 V Power Sequencing Circuit Using a Linear Regulator ......199
11-26 Another Example 1.8 V/3.3 V Power Sequencing Circuit ................................. 200
11-27 Example 3.3 V/V5REF Sequencing Circuitry .................................................... 201
11-28 3.3 V PCI/PCI-X (VCC3_3) Capacitor Placement on Backside ........................ 204
12-1 Proper Decoupling Capacitor Placement with Respect to Vias ........................ 206
12-2 Serpentine Routing ........................................................................................... 207
12-3 Serpentine Spacing - Spacing to Reference Plane Height Ratio ...................... 207
12-4 Spread Spectrum Modulation Profile ................................................................ 209
12-5 Impact of Spread Spectrum Clocking on Radiated Emissions .......................... 210
12-6 Cancellation of H-fields through Inverse Currents ............................................ 210
12-7 Length Tuning Parameters................................................................................ 212
12-8 Signal Length Solution Space with One Strobe ................................................ 213
12-9 Signal Length Solution Space with Two Strobes .............................................. 213
12-10 Signal Length Solution Space with Maximum Tolerance Strobes..................... 214
12-11 Signal Length Solution Space with Matched Strobes ....................................... 214
12-12 Total Signal Length with Two Components....................................................... 215
12-13 Package Trace Length Differences................................................................... 218
12-14 Example of PLC Compensation on the Motherboard........................................ 219
12-15 Final Illustration of PLC and SI Length Matching .............................................. 220
Tables
1-1 Reference Documents ........................................................................................ 20
1-2 DDR and Processor Bus Supported Speeds ...................................................... 21
1-3 Intel
®
E7500 and E7501 Chipset Lock Step Requirements ................................ 22
1-4 Processor Feature Set Overview ........................................................................ 23
1-5 Platform Peak Bandwidth Summary ................................................................... 26
3-1 Board Requirements ........................................................................................... 34
3-2 Assumptions for System Placement Example .................................................... 37
3-3 Entry SSI Main Power Connector Pinout ............................................................ 43
3-4 Entry SSI +12 Volt Power Connector Pinout....................................................... 43
3-5 Entry Auxiliary Signal Connector Pinout ............................................................. 44
3-6 Cooling Fan Pinout.............................................................................................. 44
4-1 CK408B Clock Groups ........................................................................................ 45
4-2 Platform System Clock-Reference ...................................................................... 46
4-3 HOST_CLK[1:0]# Routing Guidelines................................................................. 49
4-4 CLK66 Routing Guidelines.................................................................................. 52
4-5 CLK33_ICH3-S Routing Guidelines .................................................................... 55
4-6 CLK33 Routing Guidelines for PCI Device Down ...............................................56
4-7 CLK33 Routing Guidelines for PCI Slot .............................................................. 57