64-bit Intel Xeon Processor MP with up to 8MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 27
Errata
U38 Upper 32 bits of FS/GS with null base may not get cleared in Virtual-8086
Mode on processors with Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T) Enabled
Problem: For processors with Intel EM64T enabled, the upper 32 bits of the FS and GS data segment
registers corresponding to a null base may not get cleared when segments are loaded in Virtual-
8086 mode.
Implication: This erratum may cause incorrect data to be loaded or stored to memory if FS/GS is not initialized
before use in 64-bit mode. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U39 Processor may fault when the upper 8 bytes of segment selector is loaded
from a far jump through a call gate via the Local Descriptor Table
Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call gate via the Local
Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and
access an incorrect descriptor in the LDT. This only occurs on an LDT with a LIMIT>0x10008
with a 16-byte descriptor that has a selector of 0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an incorrect
descriptors within the LDT, potentially resulting in a fault or system hang. Intel has not observed
this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U40 Loading a stack segment with a selector that references a non-canonical
address can lead to a #SS fault on a processor supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a
selector which references a non-canonical address will result in a #SS fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
U41 FXRSTOR may not restore non-canonical effective addresses on
processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
enabled
Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may
store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR
instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the
FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault.
Workaround: Software should avoid using non-canonical effective addressing in Intel EM64T enabled
processors. BIOS can contain a workaround for this erratum removing the unintended #GP fault on
FXRSTOR.
Status: For the steppings affected, see the Summary Table of Changes.