64-bit Intel Xeon Processor MP with up to 8MB L3 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 8 MB L3 Cache Specification Update 13
Summary Table of Changes
U51 X No Fix A32_MCi_STATUS MSR may improperly indicate that additional MCA information may have been
captured
U52 X No Fix With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP Exception may tank single
step trap before retirement of instruction
U53 X No Fix PDE/PTE loads and continuous locked updates to the same cache line may cause system livelock
U54 X No Fix Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may update memory
outside the BTS/PEBS buffer
U55 X No Fix The base of an Local Descriptor Table (LDT) register may be non-zero on a processor supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
U56 X No Fix L-bit of the CS and LMA bit of the IA32_EFER register may have an erroneous value for one
instruction following a mode transition in a Hyper-Threading enabled processor supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
U57 X No Fix Control Register 2 (CR2) can be updated during a REP MOVS/STOS instruction with fast strings
enabled
U58 X No Fix REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang
U59 X No Fix An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to completion
or may write to incorrect memory locations on processors supporting Intel
®
Extended Memory 64
Technology (Intel
®
EM64T)
U60 X No Fix An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may cause a
system hang on processors supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
U61 X No Fix The IA32_MC0_STATUS/IA32_MC1_STATUS/ IA32_MC4_STATUS Overflow Bit is not set when
multiple un-correctable machine check errors occur at the same time.
U62 X No Fix Disabled correctable machine check errors may be logged as disabled uncorrectable errors
U63 X No Fix Machine check registers may contain incorrect information if a correctable error is followed by a
un-correctable error
U64 X No Fix Deferred Phase Support (DPS#) and Deferred Enable (DEN#) are asserted when Branch Trace
Messages (BTMs) are issued
U65 X No Fix A data Access which spans both the canonical and the non-canonical address space may hang
the system
U66 X No Fix A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly in the Branch Trace
Store (BTS) Memory or in the Precise Event Based Sampling (PEBS) memory record
U67 X Plan Fix It is possible that two specific invalid opcodes may cause unexpected memory accesses
U68 X No Fix At core-to-bus ratios of 16:1 and above Defer Reply transactions with non-zero REQb values may
cause a Front Side Bus stall
U69 X No Fix The processor may issue Front Side Bus transactions up to 6 clocks after RESET# is asserted
U70 X No Fix Front Side Bus machine checks may be reported as a result of on-going transactions during warm
reset
U71 X No Fix Writing the Local Vector Table (LVT) when an interrupt is pending may cause an unexpected
interrupt
U72 X No Fix The processor may issue multiple code fetches to the same cache line for systems with slow
memory
U73 X No Fix Starting BCLK prior to VCC being stable may cause start up problems with PLL
U74 X No Fix IRET under certain conditions may cause an unexpected Alignment Check Exception
U75 X No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address translations.
U76 X No Fix Writing shared unaligned data that crosses a cache line without proper semaphores or barriers
may expose a memory ordering issue.
Errata (Sheet 3 of 4)
No.
C-0/
0F41h
Plans ERRATA