64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update

64-bit Intel
®
Xeon
®
Processor MP with up to 1 MB L2 Cache Specification Update 33
Errata
A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64 boundary
(Intel EM64T mode), and write memory outside of the BTS/PEBS buffer.
Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EM64T mode), and
defines the buffer such that it does not hold an integer multiple of records can update memory
outside the BTS/PEBS buffer.
Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is
integer multiple of the corresponding record sizes as recommended in the IA-32 Intel® Archi-
tecture Software Developer’s Manual, Volume 3.
Status: For the steppings affected, see the Summary Table of Changes.
J56. L-bit of the CS and LMA bit of the IA32_EFER register may have an
erroneous value for one instruction following a mode transition in a
Hyper-Threading Technology enabled processor supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: In an Intel EM64T enabled Processor, the L-bit of the Code Segment (CS) descriptor may not
update with the correct value in an HT Technology. This may occur in a small window when one
logical processor is making a transition from a compatibility mode to a 64-bit mode (or vice-versa)
while the other logical processor is being stalled. A similar problem may occur for the observation
of the EFER.LMA bit by the decode logic.
Implication: The first instruction following a mode transition may be decoded as if it was still in the previous
mode. For example, this may result in an incorrect stack size used for a stack operation, i.e. a write
of only 4-bytes and an adjustment to ESP of only 4 in 64-bit mode. The problem can manifest itself
on any instruction which may behave differently in 64-bit mode than in compatibility mode.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
J57. Control Register 2 (CR2) can be updated during a REP MOVS/STOS
instruction with fast strings enabled
Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast
strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging
event, normally invisible to the user. Any higher priority architectural event that arrives and is
handled while the interim paging event is occurring may see the modified value of CR2.
Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not
observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
J58. REP STOS/MOVS instructions with RCX >= 2^32 may cause a system hang
Problem: In IA-32e mode using Intel EM64T-enabled processors, executing a repeating string instruction
with the iteration count greater than or equal to 2^32 and a pending event may cause the REP
STOS/MOVS instruction to live lock and hang.
Implication: When this erratum occurs, the processor may live lock and result in a system hang. Intel has not
observed this erratum with any commercially available software or system.
Workaround: Do not use strings larger than 4 GB.
Status: For the steppings affected, see the Summary Table of Changes.